Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

Unable to load FPGA image from the prom

Hello, I am trying to debug a scenario where I am unable to upload the FPGA image from the prom to the FPGA. The image...
1 comments posted 19yrs
posted by kjasapara
1 comments posted 19yrs posted by kjasapara

How to develop STM-16 framer in FPGA

Hi everyone, I am working on my brother's school project to develop a STM-16 framer in FPGA but I have no idea about SO...
2 comments posted 19yrs
posted by thuyp
2 comments posted 19yrs posted by thuyp

Which is your favorite FPGA language?

Hi guys, I'm currently running a series of polls on Verilog, SystemVerilog, VHDL, and SystemC. I'd like to get you guys...
13 comments posted 19yrs
posted by ngsayjoe
13 comments posted 19yrs posted by ngsayjoe

Understanding something in a bsdl file

I am converting a bsdl file to a private object format. The new thing this time are some entries which are fairly obvio...
0 comments posted 19yrs
posted by dp
0 comments posted 19yrs posted by dp

MPMC2 for Virtex-5 when?

hi any release date for new version of MPMC2 and/or udpate for Virtex-5 support? I would like to test drive it on ML505...
0 comments posted 19yrs
posted by Antti.Lukats
0 comments posted 19yrs posted by Antti.Lukats

Master IPIF interface

I have read the posts about setting up a master interface for the opb- bus. But unfortunately I am not able to realize...
0 comments posted 19yrs
posted by vimes_ankh
0 comments posted 19yrs posted by vimes_ankh

PETALINUX-COPY-AUTOCONFIG ERROR

Hello, I am trying to compile petalinux, but when I try to do "petalinux-copy-autoconfig", an error appears. The proble...
1 comments posted 19yrs
posted by pbantunez
1 comments posted 19yrs posted by pbantunez

Picobalze in the FPGA

Hi people, i am a new person in the FPGA field. I have just made something with IC from Xilinx( just make a FPGA'sboard...
10 comments posted 19yrs
posted by creativeperson8584
10 comments posted 19yrs posted by creativeperson8584

Problem with floating inputs on LVDS ports

Hello, I have a design with several LVDS transceivers. The design works well when all ports are connected but once some...
6 comments posted 19yrs
posted by Magne.Munkejord
6 comments posted 19yrs posted by Magne.Munkejord

Weird problem with WP 9.1sp1 and XC95144XL

Hi, I've got a really strange problem with a XC95144XL. It's a simple design, all schematic based, and the device is no...
4 comments posted 19yrs
posted by gavin.melville
4 comments posted 19yrs posted by gavin.melville

FPGA configuration direct from PLX

Hi, My apologies if this has been covered elsewhere - I did look! I am trying to configure a Virtex 4 FPGA from a PLX 9...
1 comments posted 19yrs
posted by rjduck
1 comments posted 19yrs posted by rjduck

CLOCK GENERATOR

Hi every body I want to creat a VHDL code in order to generate 576 clocks. The range of clocks frequency is [3 kHz to 7...
2 comments posted 19yrs
posted by saghaian
2 comments posted 19yrs posted by saghaian

substracting a whole array of values at once

hi, i need a whole matrix to be substracted form another in one clock cycle. and i need to store all the values of thes...
22 comments posted 19yrs
posted by manusha
22 comments posted 19yrs posted by manusha

chipscope + mdm with microblaze ..

Hi all, I'm having some trouble when trying to work with chipscope and mdm. It goes like this - I have a microblaze des...
3 comments posted 19yrs
posted by me_2003
3 comments posted 19yrs posted by me_2003