Weird problem with WP 9.1sp1 and XC95144XL

Feb 12, 2007 4 Replies

Hi,



I've got a really strange problem with a XC95144XL. It's a simple design, all schematic based, and the device is not behaving -- but only sort of. Pins that are unused are turning into weak outputs, some outputs work, and other don't (they may be high or low). I have data buses with 6 out of 8 pins working. Change something and recompile, reload and the results will be different eg. same data bus but now 5 pins work correctly and 3 are high or low. Most of the internal logic seems to be working OK -- this only seems to affect IO pins.



I've checked:



All pins (this is a TQ100 if that matters), including VCC/GND. A few pins ar "fast", most are not, and the 3.3 V supply looks fine. The download from a Parallel IV cable is verifyable, and repeated downloads work (or fail to work) the same. All the Fitter / Placer warnings make sense. The equations in the reports are all correct.



If I add some unneeded logic ie. add a counter, clock it and feed one output to an unused pin then the symptoms change.



Yes -- I do have it setup for the correct device.



Any bright ideas (or even some really silly ones)



While I hopefully wait for those I'm downloading 8.2 again.....



TIA, Gavin Melville gavin.melville@acclipse.co.nz

If you have an older design iteration archived, you could download that to check all the hardware is OK ?

You have checked the fitter pin-report to make sure it is not moving pins about ?

There have been other postings here about Xilinx CPLD flows, which suggest their PLD regression testing is, shall we say, "Casual".

-jg

Not for that device -- the design got too big. The smaller one was done with 8.2.03, and I've downloaded that now -- I'll try it tomorrow.

Yes I have. In some ways it's stranger than that -- take two pins that should be a CPU databus (but are actually permanently low) -- if I ground (internally) either one, the other works, however if I pull either to VCC the other stays grounded.

As a user of about 10 different versions from DOS Viewlogic forward I've never noticed that before. I've always found the software to be rock solid, well tested and clearly documented ;-)

The problem I had with a 9536 was "solved" by setting FSM extraction to no in the Xilinx tool. I also got a report that enabling WYSIWYG mode helped but I did not verify that myself since I had already gotten the design to work.

/Andreas

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required