Hi everyone,
I am working on my brother's school project to develop a STM-16 framer in FPGA but I have no idea about SONET so I am really appreciated if you can give me some instruction or idea to do it. There is also one question for the project "What are the main functions and how do you test it ?"
Regards Thuy
It's been a few years since I was working with SONET/SDH (OC-48 is SONET parlance and STM-16 is SDH last I knew).
You need:
1) Frame detection (looking for a specific unscrambled bit sequence at the same location frame after frame) 2) (De)scrambler 3) Payload insert/extract along with the specified speed-adjustment mechanism to keep the payload frequency independent of the STM-16 rate.I'm assuming you already have the physical layer including clock extraction.
What are you framing? Different payloads have different requirements. The appropriate specs will guide you to what you need for your various payloads including the rate adjustment mechanism is applicable. Packet based protocols may not need the speed adjustments I had to contend with for delivering lower-speed tributaries on the STM-16.
Just get the ITU-T G.707 document first and read it trough. It is quite well written and about 180 pages long. I'd say it is impossible to develop a STM-x framer without reading the basic standard about the frame structure.
If you need to process error conditions, pointers etc. G.783 might be a good starting point (~300 pages).
--Kim
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