Hi,
My apologies if this has been covered elsewhere - I did look!
I am trying to configure a Virtex 4 FPGA from a PLX 9656 using the two Useri/o pins in SelectMAP8 mode. I can use one to monitor the DONE bit and one to drive the RDWR line. My problem is I am not sure how to generate the CCLK to the FPGA so the config data is latched correctly,
anybody tried this?
thanks, jim