Field-Programmable Gate Arrays

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Spartan3AN - Roadmap

Hi, I just got a newsletter stating the Spartan3AN being available now. While these Spartan3AN are market as "new non-v...
22 comments posted 19yrs
posted by carlhermann.schlehaus
22 comments posted 19yrs posted by carlhermann.schlehaus

DCI termination mismatch error reported in ise91

Hi : i am using ise 9.1i to run my designs which containted lvds . In my ucf file , there are constrains like NET "Ring...
0 comments posted 19yrs
posted by black.huang
0 comments posted 19yrs posted by black.huang

Query regarding Project.Plz help very urgent

Hi, I m doing a project on "IEEE 802.3 Packet generator on FPGA".The details of my project are as follows There are two...
9 comments posted 19yrs
posted by pra.vlsi
9 comments posted 19yrs posted by pra.vlsi

Where do I find CMOS image sensors and lenses?

Hi everyone, I would to interface a CMOS image sensor to my FPGA. I'm looking for low-end sensor and a matching lens. N...
7 comments posted 19yrs
posted by it.stein
7 comments posted 19yrs posted by it.stein

No Clock in ChipScope Pro Analyzer

I setup a CDC test configuration using ILA in Chipscope Pro ver 8.1.03i. There is activity on bus and on data lines in...
4 comments posted 19yrs
posted by yaseenzaidi
4 comments posted 19yrs posted by yaseenzaidi

Routing problem of DCM

Hello, all: When I did the implementation of my design, the map process gave me the following error:...
8 comments posted 19yrs
posted by pang.dudu.pang
8 comments posted 19yrs posted by pang.dudu.pang

ISE & EDK on 64 bits linux machines - install story ;)

Hi, I've just installed a brand new machine running Gentoo AMD64 with a 64 bits kernel and a 'multilib' userland. (That...
0 comments posted 19yrs
posted by tnt-at-246tNt-dot-com
0 comments posted 19yrs posted by tnt-at-246tNt-dot-com

Xilinx Ise 6.3i

Hello, does anybody know how can I get xilinx ise 6.3i? I have installed ise v8.1i, but know in my organization I need t...
1 comments posted 19yrs
posted by pbantunez
1 comments posted 19yrs posted by pbantunez

A Very good VLSI Chip design website

Hi Designers, The website dedicated for we(VLSI Chip designer's discussing about trade-off's /problems solutions/ FAQ's...
2 comments posted 19yrs
posted by chipdesignart
2 comments posted 19yrs posted by chipdesignart

VHDL and Latch

Hi, I am very confused with latch generation in VHDL. 1. I have been using VHDL for 7 years and I have never met a situ...
37 comments posted 19yrs
posted by wtxwtx
37 comments posted 19yrs posted by wtxwtx

Multiple devices within one ISE project

Is it possible to use an ISE project to compile for multiple devices? I happen to have a project that can target two di...
6 comments posted 19yrs
posted by jean.nicolle
6 comments posted 19yrs posted by jean.nicolle

Xilinx: it's about time!

http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3an_fpgas/index.htm
0 comments posted 19yrs
posted by google
0 comments posted 19yrs posted by google

EDK 9.1 when?

Anyone knows when we will be seeing this? Thanks, /Mikhail
3 comments posted 19yrs
posted by mbmsv
3 comments posted 19yrs posted by mbmsv

Ise foundation and Ise Webpack

Hi, does anyone know the difference between Ise Foundation and Ise Webpack?. I have Ise Webpack installed in my PC and...
1 comments posted 19yrs
posted by pbantunez
1 comments posted 19yrs posted by pbantunez