Spartan3AN - Roadmap

I personally see the FPGAs following a road that leads them to looking a lot like microcontrollers but with FPGA fabric where the processor is.

---Matthew Hicks

Most of the FPGA architectures I know of, all load the config : I'm not sure even anti-fuse devices have the fuses actually in the signal path. (imagine the tpd cost, of those fuse-program circuits ! )

So, what we are really talking about, it the time taken to load the config. Some are largely parallel, some are parallel-serial, and some are pure serial (3AN).

I see your point, and "loader included" might be more accurate than "new non-volatile", as that claim also implies a certain security level that other "non-volatile" alternatives DO offer.

I thought ADCs were already in FPGAs, but targeting temperature and Vcc verification tasks, not mUXd to Pins (die is likely to be rather noise for that..? )

-jg

Hi Jim, The Virtex-5 is the first Xilinx device to support an ADC, and most other FPGAs (and FPGA companies!) don't have integrated ADC's at all. The Virtex-5 System Monitor solution has an ADC core (200K/s), with internal voltage sensors (Vccint and VccAux), and Temperature, plus a dedicated high bandwidth input channel, and 16 channels that are optional digital or analog IO. So no valuable pins used, unless you want to.

To answer your question on noise: noise performance is very good, due to all input channels being fully differential (and there is support for bipolar and unipolar signals on all input channels). Also, due to the speed of the ADC, and to further suppress noise, averaging can be turned on for every channel, while still maintaining a high sample rate.

Other features include automatic sequencing of the channels, and alarms are available to warn you if the internal sensors detect dangerous voltage/temperature conditions.

For more info see:

Or UG192:

Plug in chipscope to a Virtex-5 FPGA and it will read back the internal voltage / temperature sensors live on a nice graph for you!

Hope this helps John

Thanks for the details - good to see it's nice and flexible.

Can you comment on the OP's question : "Any truth in rumors stating next generation Spartan (or what it will be called) has integrated Analog-Digital Converters? "

- would seem likely, once a block is finally proven on a process, all the hard work is done.

-jg

Jim,

That is true.

If enough customers when surveyed answered that the "system monitor" added value to their devices, then I am sure the block is under consideration for inclusion.

The real difficulty is that this block consumes area which is wasted for anyone who doesn't need it.

With the constraints on pricing for Spartan parts, cost is everything.

This also presumes that there will be a new Spartan part on 65nm, and exactly how this is featured is not something we can discuss here. Does it favor lower static power at the cost of system speed? Or, does it have medium speed, and medium static power (and no one is happy)?

As you may be well aware, the ITRS roadmap has some serious issues:

and even more depressing:

Technology has slowed to a crawl: three years between nodes is now the optimistic prediction. Speed is hardly faster, leakage is far worse, dimensions can not be made smaller (unless you don't care about yield). The 'fast' train has hit the "foothills" and we need to do more than just make everything smaller (and get speed, power, and cost improvements). We now have to consider what our customers need (wow, what a concept!), and decide how we may be able to add value.

Triple oxide, strained silicon, strained Ge-Si, silicon on insulator, multiple voltages, multiple Vt's for nmos and pmos: the toybox is empty. We have no hi-K gate dielectric (yet). How do we 'improve'?

Even Intel and AMD have completely revised their stories: it is no longer about clock speed but "multicore" and "multicore+graphics processor." I have heard at a conference someone ask the Intel presenter "isn't where you are going where FPGAs have already been?"

Austin

You are right, tho some milestones are pushed out, as they prove less essential than some believed :

450mm wafers is one (if die sizes are not going up, why should wafers ? ), and immersion is delayed by advances in masking

and then, other technolgies suddenly look closer

This in todays news :

?articleID=197800524

"..sample a 90-nm 128-Mbit phase change memory to customers in the first half of 2007. Mass production could begin before the end of 2007 the chip giant said."

I have to be impressed - remember, this is intel (!), and aren't those times lines quite similar to today's just-sampling FPGAs ....

So, I went looking for speed info, and found this

:However, he did say that PRAM's random read access latency is very :comparable to DRAM. "Phase change memory fundamentally has a very fast :read speed, and how the bandwidth is depends on how it's configured in :the actual end product," said Kimoto.

PRAM does not show in the foundries plans at moment, but a stacked die PRAM + FPGA, with wide access bus, would be near term do-able : mainly dependant on the FPGA volumes being large enough to interest the big memory players...

-jg

Jim,

As I said, how do we IC designers "add value?" If the ITRS mad dash has slowed to a crawl, other technologies might 'catch up' and actually become useful.(!)

We used to complain that we didn't have time to mess with dram+logic (or eprom+fpga: put you favorite combination here) on the same device, maybe now we do?

Austin

Hi, as Peter already wrote, the difficulty of implementation of ADC is to decide what application is to be targeted. I also recognize the problems of high-speed, high precise and high bitwidth ADCs may be distorted by the noise on the digital chip. I think those ADCs would have to be separately powered and accuratley decoupled from the digital part of the FPGA. In case the ADCs are targeted for temperature and sytem internal voltage monitoring, they are normally not that high sophisticated ones (the measured parameters won't change that quick, nor is a 12bit precision necessary. Those ADC may be implementable easier, while for e.g. brushless motor controllers those ADC's performance may not meet the control loop requirements (phase current measurement precision and sample rate). In case these ADCs are attached as separate ICs, they are easily selectable to suit the intended application's requirement perfectly. I was just curious for future trends re. more functions to be integrated in one FPGA "housing".

Greetings, Carlhermann

I read this back along about Intel's hafnium based high-k material. Is that one of the hi-k materials that FPGA manufacturers have tried already?

Thanks, Symon.

Un bel giorno Jim Granville digitò:

Actually I think that Actel antifuse FPGAs are made that way (otherwise it wouldn't make much sense to differentiate between "flash" and "antifuse" FPGAs, like Actel does).

See for example

page 7 and following.

I agree with the OP, in my opinion defining S3AN as "nonvolatile" is quite inaccurate. Maybe it isn't misleading for an engineer (it's very clear, starting from the name, that the S3AN is just the usual SRAM device with a boot flash embedded), but it could be misleading for a IT manager that takes decisions about things he doesn't know (i.e. the 95% of the grand total).

--
emboliaschizoide.splinder.com

Symon,

Intel is keeping this secret. If true, it is a huge improvement, and one that the foundries will be itching to get their hands on.

The hi-K dielectric for the transistor will keep the roadmap moving forward with lower leakage (the gates leak at 65nm and below), and perhaps better speed (hi-K makes the transistor stronger according to Intel).

Austin

I don't remember where I first saw it mentioned, but they are not keeping it a secret. Here are a few mentions about it:

And here is the leading supplier of it:

Regards,

John McCaskill

I guess Austin means they're keeping the process details secret, not the results. Go to the above link you posted on intel.com and search for 'secret'! ;-) HTH, Syms.

For a delta-sigma converter, I don't believe this is true.

Its hardware is fundamentally a very fast, low-resolution (typically

1-bit!) ADC, coupled to a similar DAC, via an n'th order filter in a feedback loop to perform noise-shaping, ie to shift quantisation noise out of the desired frequency band into another part of the spectrum.

This has to be followed by a band-limiting filter (in the digital domain), normally accompanied by decimation to the sample rate of interest.

The dumbest implementation, a first order high pass filter in the feedback loop, is recognisable as an integrator - but typically a third order filter is employed.

Now it's been a long time since I read Bob Adams' papers, but reading between the lines it seemed obvious that you could choose the noise-shaping filter to suit your application, selecting different ones for extremely low noise in a narrow bandwidth, or higher noise levels in a wider band, the product of the two parameters being roughly constant. The bandlimiting/decimation filter obviously has to track this choice. (Selecting between filters is safer than full programmability, a poor choice of filter in a feedback loop leads to instability!)

- Brian

The parts aren't "available now." (We'd like to see the smaller 3A parts ...)

Anyways, the Lattice XP devices, which have been around for quite awhile, have built-in configuration flash memory and start up a lot quicker than the 3AN devices. I haven't done a detailed side-by-side feature comparison, but it looks like one Xilinx advantage is that their flash can be used for both configuration and as part of the design; the Lattice memory is for configuration only. I dunno who's faster, who's got more resources, who's less expensive, etc.

I do recall certain Xilinx representatives saying something like "on- board configuration memory means that we'll have to use an older process, meaning slower, more power-hungry parts, yadda yadda yadda."

-a

That was refering to same-die configuration; the process constraints go away then you deploy 2 die in one package, which is what Xilinx have done.

Some companies simply wire bond the second die in a spare area, in BGA that's easy - just design the BGA paddle & pgm the bonding machine.

Others are working on flip-chip bump bonding, where the die is designed to take the daughter chip, and the bonding costs drop (not just $, but area/height costs too ) and you can get a lot of contacts going between the die. If you are already doing flip-chip onto the BGA, to get die-wide bond pads, and lower nH, then it's somewhat harder to find a place to put the second memory die .....

-jg

Perhaps that is what he meant, but I would expect that either Intel would licence their technology after a while, or the IBM/AMD/Sony/ Toshiba group will.

If none of them want to license it, I didn't want it anyway. After all, hafnium is only half as good as unobtanium which is used in all the best -K dielectrics.

Regards,

John McCaskill

"I personally see the FPGAs following a road that leads them to looking a lot like microcontrollers but with FPGA fabric where the processor is."

.... Wrong way around... FPGA fabric where the controllers are, hard silicon where the processor is... and they've already done this... virtex FX series parts - powerPC in hard silicon, runs the speed of a power pc in hard silicon (fast) surrounded by FPGA fabric that you can do whatever you need to with....