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Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes

Hi guys

I'm trying to synthesize processor core with ROM and RAM in the VirtexE FPGA.

I've created RAM memory using VirtexE Block RAM resources by means of 'Single-Port Block Memory Core Generator' in Xilinx ISE.

My problem is that VirtexE memory supports only 'Read-after-Write' mode. In this mode, what has been written to the memory is transferred on the active clock edge to the output port of the memory immediately after assertion of 'Write Enable' input.

I need to interface this memory to the processor which accepts all values coming from the RAM, therefore 'No-Read-on-Write' mode, where input data are not transferred to the output of the memory after successful write, should be used.

'Read-after-Write' causes invalid values to be transferred to the processor after each write to the RAM.

Does anyone know how to overcome this problem?

Thanks! Wojt

Reply to
wojt
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Rearrange the transfer to the processor.

Even in the "NO_CHANGE" write mode in the more recent FPGAs, there's SOMETHING on the BlockRAM output. It may be last cycle's data but it's only the data, no address to accompany it.

How can having a data word for an unused cycle showing up on the BlockRAM output be a problem in your system?

To mimic the NO_CHANGE format, you can always use latches; the latches are clear during reads but maintain the previous value during writes. I still don't see how this "do nothing" state will help you in your quest.

Reply to
John_H

Reply to
Peter Alfke

Hi Wojt,

  1. 'Single-Port Block Memory' means the RAM block cannot do read and write at the same clock. If your design cannot guarantee this principle, your choosing single-port is wrong and you have to switch to dual-port block memory ram.

  1. Whether single-port or dual-port block memory ram is used, you must design an interface between your processor and the block memory ram to guarantee that write and read work normally as you desire.

  2. The most important thing you have to do now is to read Xilinx materials thoroughly and carefully and understand every technological details, otherwise you are doomed to a failure.

  1. Xilinx block ram is very well designed and works excellent in my experiences with it.

Weng

Reply to
Weng Tianxiang

This is a wrong statement. Each port of the BlockRAM has independent write and read data lines. When data is being written into the port (WE active) then the data output has 3 choices: either reflect the data being written (write first) or reflect the previous content of the addressed location, before it was being overwritten (read first) or keep the output the way it was (no change) This describes Virtex-4 and Virtex-5 BRAM behavior. Older Virtex BRAMs do not have the read-first option. The other memory port has the same array of choices, since the two ports are independent, sharing only the stored data. Only when both ports happen to address the same location, is the timing somewhat demanding... Peter Alfke

Reply to
Peter Alfke

Hi Peter, You are right.

I mixed two things: single-port distributed ram and dual-port distributed ram with their block ram.

My claim is true when read and write cannot happen at the same clock with single-port dristributed ram, not with single-port block ram.

I have just finished a new project successfully that uses single-port distributed ram and purposely added logic to avoid read and write from happening at the same clock.

Thank you.

Weng

Reply to
Weng Tianxiang

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