Hi,
I m doing a project on "IEEE 802.3 Packet generator on FPGA".The details of my project are as follows There are two swithes on the FPGA to input 4 different lengths of data between 0 to 1500bytes.if a particular input is set, for eg
60bytes,then the controller should generate data of 60 bytes.so, i need to design a generalised controller that will accept data of 4 different lengths and generate the data depending on that length.i have to write a code in vhdl.Plz help me to design the controller
I m not getting data from any source.i have to generate random data.Its something like i m developing a smart bits generator on FPGA.I have to generate the data in IEEE 802.3 format.So, the controller which is to b designed has to send the control and timing signals to activate the different fields in the frame format.Different fields in the sense first preamble should come which should b of
7bytes.Then start of frame delimiter and so on.
But one thing i want to know is whether i need to design a random number generator for generating data or there is any other method to generate rendom data.And after generating the data,do i need to store that in a memory and then transmit?Do i need to generate the preamble also? Please give me guidelines for finalising the designs
Is the spec what i have got is enough?? If not,then what else is required? it might b a silly question.I m a fresher so i dont have an idea of whatelse is required.plz help me.
Plz help me in this regard. Plz Its very urgent
Thanks