Query regarding Project.Plz help very urgent


I m doing a project on "IEEE 802.3 Packet generator on FPGA".The details of my project are as follows There are two swithes on the FPGA to input 4 different lengths of data between 0 to 1500bytes.if a particular input is set, for eg

60bytes,then the controller should generate data of 60 bytes.so, i need to design a generalised controller that will accept data of 4 different lengths and generate the data depending on that length.i have to write a code in vhdl.Plz help me to design the controller

I m not getting data from any source.i have to generate random data.Its something like i m developing a smart bits generator on FPGA.I have to generate the data in IEEE 802.3 format.So, the controller which is to b designed has to send the control and timing signals to activate the different fields in the frame format.Different fields in the sense first preamble should come which should b of

7bytes.Then start of frame delimiter and so on.

But one thing i want to know is whether i need to design a random number generator for generating data or there is any other method to generate rendom data.And after generating the data,do i need to store that in a memory and then transmit?Do i need to generate the preamble also? Please give me guidelines for finalising the designs

Is the spec what i have got is enough?? If not,then what else is required? it might b a silly question.I m a fresher so i dont have an idea of whatelse is required.plz help me.

Plz help me in this regard. Plz Its very urgent


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I wouldn't be too hopeful of getting any data with this type of posting either!

But wait, perhaps you could generate random data from the content of homework questions posted on usenet. The sheer cheek of students asking folks to do their work for them for free implies a randomness of thought which should be reflected in their postings. Also, their spolling and caPITaliSation is atroshus, which should plz your rendom nuber generator. Lots of love, Syms.x

p.s. For anyone who's interested in a proper random number generator, a search for

random webcam smoke alarm

gives interesting results.

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I was sure you were just joking, but that *is* fairly interesting!

Alan Nishioka

Reply to
Alan Nishioka


A bit on the slow side, but it sure is random!


Reply to
Austin Lesea

just get a stronger americium source :p

is it just me or is usenet getting full of asian sounding names with gmail accounts asking for complete solutions to problems they have hardly tried to understand themselfs ?


Reply to


As far as I am concerned, the questions come from students of engineering who will someday soon be designing with FPGAs. I would hope they consider Xilinx when they make their choice of vendors.


Reply to
Austin Lesea

Not just that. More often, we'r seeing images in media of asian- looking chap staring at a PCB or something in indication of "cutting- edge" intelligence to which everybody should aspire. Even empolyers are becoming more inclined to believe in you provided that you possess "certain" attributes.



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See the reference design and testbench here

formatting link
for some related examples.

You will have to learn vhdl simulation. It sounds to me like you are in water over your head. Consider dropping the class.

-- Mike Treseler

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Mike Treseler

This is not the way to answer questions.

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This is not the way to ask question. Tell us

- more about your problem

- what you already did yourself

- where you met problems

then somebody might be willing to help you. The readers of this group are not required to help you. Mostly the will help, if they find the problem interesting and the poster doing most of his homework himself.

B.t.w. where did you struggle with a google/altavista/.. search for some/all of the words FPGA Random HDL VHDL verilog?

Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Uwe Bonnes

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