Systemverilog preprocessor allow "..."?

ANSI-C preprocessor supports a 'wildcard' ... #include

#define _NOISY_PRINTF( ... ) printf( ... ) #define _QUIET_PRINTF( ... )

int main( void ) { _NOISY_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 ); // hello world, 1, 2, 3! //

_QUIET_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 ); // // }

I don't suppose Systemverilog's preprocessor supports this? (And I assume SystemC has no trouble with it...)

Reply to
Ulsk
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Ellipsis(...) is a defined stuff in ANSI-C. I doubt if it is so in SystemVerilog.

Reply to
aniruddha.nag

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