Latest threads in Field-Programmable Gate Arrays

How is it possible to design a convolutional interleaver with sequential memory writes?

In my interleaver design for FPGA, I am using an external SDRAM for data storage. The clock cycles required to write a...

4 19yrs

newsreader

4 19yrs newsreader

Compiling simulation libraries of EDK 8.1.02i under Linux

Hello everyone! I try to compile the EDK 8.1.02i simulation libraries with its wizard under Fedora Linux. My problem is...

1 19yrs

dtheodor

1 19yrs dtheodor

LC8

http://forum.lc8.info/viewtopic.php?p=113147#113147 - Philip -- A PERSON is smart. PEOPLE are dumb, panicky, dangerous a...

0 19yrs

phq

0 19yrs phq

Confuse on Spartan speed

Hello everyone, Please help. What is the maximum clock frequency that can be used on a Spartan-3 5000? I know it's a gra...

6 19yrs

yasirmm

6 19yrs yasirmm

is edk 8.1 availabe for download

hi all i am mahalingam, student from univ of south florida. i am using xilinx ise 8.1 and virtex ii pro 2vp30 board for...

1 19yrs

mahalingamv

1 19yrs mahalingamv

ANNC: Tips for FPGA Timing Closure Webcast

Lattice is holding a webcast Tomorrow Wednesday, Mar 28, "Tips for FPGA Timing Closure." The presenter will be Troy Sco...

0 19yrs

bart.borosky

0 19yrs bart.borosky

What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L

Hi, When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would like to know which patents filed by Xilinx t...

8 19yrs

wtxwtx

8 19yrs wtxwtx

longest webcase record

> JTAG BPI S3E issue - there is a solution that fixes the problem > the external flash memory can be put into status re...

0 19yrs

daughenbaugh

0 19yrs daughenbaugh

(Xilinx) OPB watchdog timer fails to release RESET

Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_tim...

4 19yrs

jshamlet

4 19yrs jshamlet

Help with Xilinx Parallel Cable IV.

I've just started a new FPGA project, and am having trouble getting the parallel cable IV to work at speed. I'm using a...

7 19yrs

pfraser

7 19yrs pfraser

Lattice "Open IP" license is GPL-compatible?

I'm working on a new project using some code from opencores for my thesis research. I'd love to use a nice, high-qualit...

4 19yrs

jonas

4 19yrs jonas

Re: EDK : Import Custom Peripheral

Figured it out on my own... EDK doesn't happily mix languages.. remade the top peripheral wrapper in VHDL instead of ver...

0 19yrs

dejanigma

0 19yrs dejanigma

PCI-Express drivers with Xilinx FPGA?

Hi guys: First of all, forgive me for being a dumb mechanical engineer...FPGA's are new to me. I'm programming a Xilinx...

7 19yrs

eromlignod

7 19yrs eromlignod

CycloneII altlvds_rx

Hello, I am using the altlvds_rx core of altera to make a video deserializer in an FPGA. I have implemented the design...

8 19yrs

Karel.Deprez

8 19yrs Karel.Deprez

Open-source CPU-core for standard-cell ASIC?

Forgive me if this topic has been beaten to death. Are there any *production-quality* open-source embedded CPU cores, t...

6 19yrs

dontreply

6 19yrs dontreply

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