We did implement your suggested work-around and it works great! Much better than the Xilinx suggested workarounds. Thanks Antti!
I have also be intermittently chasing this issue through Xilinx. I finally got an answer today. They confirmed that this problem does still exist in stepping 1. They have decided not to fix this problem in hardware (since their first attempt failed), but rather make a software change. The latest version of iMPACT has this fixed, ISE9.1.01i. (Our JTAG guy does think that their software fix is sound, although we have not tried it in our software). They have an answer in their database, 22255, which gives more detail on this problem.
I opened this case over six months ago, and they were able to reproduce the problem, yet they still have not publicly acknowledged that this problem still exists with stepping 1. In fact, they still state that it does not exist in stepping 1. Wrong information is worse than no information!
The datasheet says: "Stepping 1 and later devices fully support JTAG configuration even when the FPGA mode pins are set for BPI mode."
and answer 22142 says: "NOTE: This issue applies to only Spartan-3E engineering samples and to the Stepping 0 devices. This is not an issue for Stepping 1 devices."
Granted, this is a small problem that likely doesn't affect many people, but it is totally unacceptable that they do not have an adequate process for fixing their documentation, even when a customer goes out of their way to try to help them fix it!
Through our Avnet FAE (who has been very helpful) I was finally able to get them to issue a CR to fix their datasheet, today, March 27,2007. Case opened August 23, 2006. Datasheet fixed sometime April 2007? Great response time! I hope others haven't wasted time with this in the interim.