In my interleaver design for FPGA, I am using an external SDRAM for data storage.
The clock cycles required to write a frame into the RAM and read a frame back to error correction unit ain't enough.
The interleaver has 40 rows, which contain 200 * 0, 1, ...39 pieces of data. And one row of the RAM contains 256 data. The write/read pointers are increased by 200*i or decreased by 200*i (0
If you write out by hand the order in which data comes out of a depth- N interleaver, you should be able to spot the pattern (it's really not a very complicated pattern...).
You can then just apply this pattern to the read pointer, letting you store your data in the original (sequential) order. In other words, the interleaving is done during the read operation.
However, the read access pattern will be just as "random" as the write access pattern was in your original design. So unless your SDRAM's read cycle is shorter than its write cycle, this won't save you any time.
-- Oli
I'm not sure how much it would help in your application unless your interleave factor is constant, but using the 4 banks of the SDRAM is generally a faster way to deal with high-speed data than attempting to locate all data in a single row. SDRAM was designed such that the row activate and precharge can be "buried" behind other operations when multiple banks are used. So in essence if you can order your storage such that each new data comes from a different bank in the SDRAM you can cut your cycle time down significantly. Using the minimum burst size (assuming you don't need more than one word of data at a time) and read with autoprecharge (to avoid the additional command to "close" the row) you can get down to 2 cycles per read if you rotate through all four banks. A control sequence for a regular rotation through 4 banks might look like:
--- Startup section with some wasted cycles --- Activate Row in Bank 0 NOP Activate Row in Bank 1 NOP Activate Row in Bank 2
--- Continuous high-bandwidth section Read Col in Bank 0 with autoprecharge Activate Row in Bank 3 Read Col in Bank 1 with autoprecharge Activate Row in Bank 0 Read Col in Bank 2 with autoprecharge Activate Row in Bank 1 Read Col in Bank 3 with autoprecharge Activate Row in Bank 2 Read Col in Bank 0 with autoprecharge Activate Row in Bank 3 Read Col in Bank 1 with autoprecharge Activate Row in Bank 0 Read Col in Bank 2 with autoprecharge Activate Row in Bank 1 Read Col in Bank 3 with autoprecharge Activate Row in Bank 2 Read Col in Bank 0 with autoprecharge Activate Row in Bank 3 Read Col in Bank 1 with autoprecharge
--- Closing section with some wasted cycles NOP Read Col in Bank 2 with autoprecharge NOP Read Col in Bank 3 with autoprecharge
Note that the mid-section can be repeated ad-naseum allowing unlimited access length at this bandwidth. Also note that each access includes its own Row and Column so other than the bank restriction the order can be truly random.
HTH, Gabor
Pipelining the four banks am I right? I will study this since this is the first time I handle SDRAM.
Thank you for the pointer.
Yeah, this is what I am looking for. For this algorithm, my question is, what is the condition when I am able to write from memory address 0 again when the first iteration is over, without overwritting the data already in the memory.
I was aware that, the read operations are with random addresses, however writes are sequential. If the write pointer flips back from upper bound to address zero too early, it may overwrite some data. How do I calculate the upper bound?
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