Hi, I'm working on a Microblaze system in a Spartan 3-2000. I am trying to implement a watchdog timer using the opb_timebase_wdt IP core. I'm currently using ISE/EDK 8.2.02i, and the WDT version is 1.00a.
The watchdog timer otherwise works fine. I can start/stop/reset the timer with no problem. The trouble is that when the watchdog timer DOES cause a reset, it won't release the reset line, which was effectively locking up the system. It did NOT respond like the datasheet.
To solve the immediate problem, I have inserted an edge detector into the reset control logic, which allows the system to reboot, but I can't get the WDT_Reset signal to go low at all. The end result is that the WDT can only reset the system once.
I did bring both signals out on test points, and I can see this behavior on a scope. The interrupt performs as expected, but once the WDT_Reset signal goes high, it stays high until I reconfigure the FPGA.
Note, I am using a custom reset controller, because the ComBlock 1200 board I'm using requires special treatment due to the clock situation. (the clock isn't stable until after configuration, causing DCM problems). Any reset input will cause both a sys_reset and dcm_reset. dcm_reset is released as soon as the reset input goes away, but sys_reset is held until the clock is stable for at least 64 clocks or so. I haven't had any other problems with this reset controller.
What am I missing here?