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Confuse on Spartan speed

It depends on what you want to do with it. If all you are interested in is one long shift register you can run it extremely fast as an approximation. If you want to run a complex superscalar microprocessor in it with a three stage pipeline then you can run it extremely slow as an approximation... Most designs will fall somewhere in between.

Remember that you are constructing a circuit here and depending on the circuit you build you will get different delays. It is totally possible to build a combinatorial path that will span every single LUT of the chip. Not a good idea, but possible :) (So I guess it would be possible to calculate a theoretical minimum frequency by doing a path which would go through every LUT and place the LUTs as badly as possible so the routing delays are maximized.)

/Andreas

Reply to
Andreas Ehliar
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Hello everyone,

Please help. What is the maximum clock frequency that can be used on a Spartan-3 5000? I know it's a grade -4 speed but I couldn't find any documentation regarding it.

-Ace-

Reply to
Ace

As stated here.... for ANY fpga, the specified Fmax is a theoretical max. Odds are you will never hit that if you are doing anything vaguely complex. That assumes your logic as pipelined to the maximum capabilities of the part - no more than one LUT of combinatorial logic before a DFF - so it makes maximum use of the CLB layout. It also assumes that routing delays are near negligible - i.e. assumes your design can be routed such that you flow from one CLB directly to the neiboring CLB. As soon as you go through more than one LUT of combinatorial logic before a flop or pack your part tight enough that your routes aren't all COMPLETELY ideal.... that is to say, as soon as you put a real design in the part, that Fmax goes down depending upon the details of your design.

Reply to
Paul

Thank you to both Andreas and Paul. After reading your feedback, can I make this conclusion "Spartan FPGA has it's own clock which can fit most design".

Reply to
Ace

Reply to
Daniel S.

Huh... I think you got it backwards.

FPGAs do not have "their own clock", you have to tell the synthesis tools what clock period you intend to operate the FPGA at unless you want the synthesis to run and optimize the design until timing improvements stall. If you place a 10ns period constraint on an input clock, the synthesis tools will tune the primitives' placement and routing until all components on each constrained clock net and derived clocks meet the specified and derived timing constraints.

The maximum operating frequencies for specific functional blocks within the FPGA and common constructs are only general indications of the highest achievable clock rates in a carefully pipelined design. Just like a chain, your overall highest operating frequency is limited by the slowest functional block or combinational construct in each clock domain. The STA ("Static Timing Analysis") will tell you what the highest operating frequencies (minimum clock periods, actually) for each of your design's clock domains are and which paths have failed to meet timing specifications.

Reply to
Daniel S.

Thanks a lot Daniel! :D I must have myself sound so naive (well I am...)

Cheers!

Reply to
Ace

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