Field-Programmable Gate Arrays

Measuring the period of a signal

Hi, I am trying to measure an input signal that will be a square wave of a certain unknown frequency in the range 1MHz...

4 comments posted 19yrs

posted by axr0284

4 comments posted 19yrs posted by axr0284

Clocking data into a shift register on positive AND negative edges

Hi, I'm trying to design a floppy disc 'raw reader' (to archive discs that have been written in unusual formats that PC...

6 comments posted 19yrs

posted by usenet07

6 comments posted 19yrs posted by usenet07

How do I use the Xilinx USB download cable for testing?

Fellow Designers, I am looking for a more convenient way to use inexpensive eval boards to test logic designs in an fpg...

6 comments posted 19yrs

posted by pete.dudley

6 comments posted 19yrs posted by pete.dudley

query

I am implementing IIR Filter in verilog with equation y(n)=a*x(n)+(1-a)*y(n-1) a is floating point no with 5 bits x is...

0 comments posted 19yrs

posted by vsrpkumar

0 comments posted 19yrs posted by vsrpkumar

Xilinx ISE constanly asking to regenerate a core file.

Hi everyone, I have a very simple ADC controller in VHDL, plus a Xilinx FFT core. There are only 2 files in my project:...

4 comments posted 19yrs

posted by pkolinko

4 comments posted 19yrs posted by pkolinko

raggedstone + xc3sprog?

Hello, all... Has anybody gotten xc3sprog to work with the raggedstone board and its included parallel programming cabl...

5 comments posted 19yrs

posted by megacz

5 comments posted 19yrs posted by megacz

A new way to define systems of systems?

I have recently been playing around with what I think is a new approach to defining and implementing distributed embedd...

16 comments posted 19yrs

posted by rich

16 comments posted 19yrs posted by rich

ispLever FTP Download

Hello... Why is it that the Windows Version of ispLever 6.1 is downloadable via FTP but not the Linux version? thx in ad...

0 comments posted 19yrs

posted by Jedi Router

0 comments posted 19yrs posted by Jedi Router

can anyone give me a reference price of the following Xilinx boards?

I can't check any price infomation about the following boards in xilinx website: 1) ML521/3/5 ---- Virtex-5 GTP charact...

4 comments posted 19yrs

posted by wicky.zhang

4 comments posted 19yrs posted by wicky.zhang

How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?

Hello, I am trying to implement an 8 bit adder program using VHDL on Virtex 2 pro with expansion kit DIO4 from digilent...

1 comments posted 19yrs

posted by chai2m

1 comments posted 19yrs posted by chai2m

XUP virtex-II pro

Hello I developed a hardware component in ISE which interfaces with my own- made print-circuit by using the lower middl...

0 comments posted 19yrs

posted by wouter.vanhauwaert

0 comments posted 19yrs posted by wouter.vanhauwaert

Icarus Verilog

I just wanted to get a heads up from anyone out there about this tool. My initial results (for some trivial designs) we...

0 comments posted 19yrs

posted by emh203

0 comments posted 19yrs posted by emh203

Nios2: elf2hex settings for epcs bootloader

Hello, I have recompiled the assembler code for the bootloader of the Nios2. After this compilation I have an .elf file...

1 comments posted 19yrs

posted by Karel.Deprez

1 comments posted 19yrs posted by Karel.Deprez

virtex 4vfx12 evaluation kit schematics

hi, can any please tell me where i can get virtex 4vfx12 evaluation kit schematics. thanks asha.

1 comments posted 19yrs

posted by ashasravanthi

1 comments posted 19yrs posted by ashasravanthi

Memory Interface Recommendation for ML410 Design

Hello, I am working on my MS Thesis which involves building a PowerPC based system on the ML410 development board from...

0 comments posted 19yrs

posted by Dmitriy.Bekker

0 comments posted 19yrs posted by Dmitriy.Bekker