Xilinx ISE constanly asking to regenerate a core file.

Hi everyone,

I have a very simple ADC controller in VHDL, plus a Xilinx FFT core. There are only 2 files in my project: ADC_control.vhd and myfft.xco

Every time I try to create a new bit file, ISE complains that it can't find myfft.v and asks to regenerate the core. It takes a long time... and is quite frustrating.

I generate myfft.vhd and myfft.xco files in the Core Generator. How do I avoid regenerating the core? Why does it keep asking me for a verilog version .v of the core?

Thanks! Pavel

Reply to
Telenochek
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Nevermind, problem solved.

Reply to
Telenochek

How about sharing your solution with the group? ;)

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Reply to
Sean Durkin

Not sure if there's an efficient way to fix it... but in my experience, this happens when you generate your core into a directory other than your root project. I used to try to have /ISEProject/Source/Coregen in my directory structure, but ISE always tried to regenerate stuff for me. The problem is solved by regenerating the core into the root directory ISEProject/ but its a royal pain if you've got a lot of files you're trying to keep straight... if there's a better solution out there I'd love to hear about it as well!

Reply to
Paul

It may be as simple as having your core files in a common directory and setting your "Macro Search Path" in... I think it's the Translate properties in the GUI. I didn't offer this suggestion straight out because I didn't see how regenerating the core would change the fact that the core isn't in a searchable location.

Reply to
John_H

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