Hi everyone,
I have a very simple ADC controller in VHDL, plus a Xilinx FFT core. There are only 2 files in my project: ADC_control.vhd and myfft.xco
Every time I try to create a new bit file, ISE complains that it can't find myfft.v and asks to regenerate the core. It takes a long time... and is quite frustrating.
I generate myfft.vhd and myfft.xco files in the Core Generator. How do I avoid regenerating the core? Why does it keep asking me for a verilog version .v of the core?
Thanks! Pavel