Hi, I'm trying to design a floppy disc 'raw reader' (to archive discs that have been written in unusual formats that PCs can't read). I've got a basically working data separator design that turns the MFM (or FM) data signal into a data output and a data window signal. This is how it looks on a logic analyser (note that the vertical : lines denote the bit cell boundaries):
__________ __________ DWIN __________| |__________| |__________ : : _ : _ _ : DATA __________________________| |_____| |_| |_____________ : : : :
clock-0 clock-1 clock-1 clock-0 (noisy)
Basically, a transition (either H-L or L-H) on the DWIN (Data Window) line denotes the start of a bit cell. If DATA is pulsed at least once within that bit cell, then a 1 should be clocked into a shift register (a 16-bit SR used to detect the synchronisation word). If there wasn't a pulse, then a zero should be clocked into the shift register.
Now the problem I have is that in Verilog (or at least Xilinx ISE8.1 Verilog) you can't trigger on both a positive and negative edge of a signal - the language allows it, but ISE complains that it can't find a matching 'FF or latch template' (error code Xst:899).
The idea I came up with was to have a D-type flip-flop wired with D=1, Q to the SR's data line, and CLK wired to a signal that pulses every time there's a DWIN edge. The problem I have is that I'm quite new to CPLDs, so I'm not sure how to go about creating the 'pulse every transition' signal.
Am I thinking along the right lines here, or is there an easier (or just another) way to do this?