raggedstone + xc3sprog?

Hello, all...

Has anybody gotten xc3sprog to work with the raggedstone board and its included parallel programming cable?

I had to add an entry to devlist.txt for the configuration PROM (xc3sprog gets upset if it sees any unrecognized devices on the chain, even if they're not the one being programmed). After doing that, I'm able to program the S3 directly like this:

./xc3sprog pci_7seg.bit 1

The board's 7-segment LEDs go blank for a while and then come back on. Here's the kicker: the board is currently running the "default" bitstream that the board ships with, which counts down in hexadecimal. After the LEDs go dark, they come back *at the same counter position they were at before programming* and continue counting down.

So, apparently the device is not only not getting programmed, but it isn't even getting reset. Yet the LEDs go dark and xc3sprog reports no errors.

Weird.

Any advice?

- a

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PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380
Reply to
Adam Megacz
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Adam

Getting the chain of JTAG devices means there is a hardware level issue and manually override won't do a lot to help.

There are a few possibilities listed on the FAQ page here

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Beyond that we occasionally see issues with noise on PC's. Using a different host to program and holding PC in reset is often enough to clear this issue. Long extension cables can also cause issues. If you still have an issue after that it might just be the programming cable is faulty and you should send an email to our board sales email and they will send out a replacement. You are not likely to get a response from them until Thursday as the sales and shipping team are shut down until then for Easter holidays.

John Adair Enterpoint Ltd.

Reply to
John Adair

By a stroke of luck, I figured it out. In order to program the board, you must add this line to devlist.txt:

f5045093 8 PROM

Previously I had been using a value of "6" (like the other entries in the file). Using "6" gives the behavior I explained before. Using "8" results in correct programming.

John, I suggest you add this to the raggedstone FAQ.

One more question: I ordered the Ethernet PHY, but the pins on the bottom of the PHY daughterboard don't match any of the headers on the raggedstone. The daughtercard has two single-pin rows, plus four additional pins that are offset diagonally from the top and bottom pin of each row. The Raggedstone has only single-pin rows, none of which appear to have a pin-hole in the diagonal position.

Am I missing something?

Thanks.

- a

"John Adair" writes:

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PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380
Reply to
Adam Megacz

Adam

You have not missed anything. The inner pins are for an enhancement of the DIL headers where we have inner strips with power pickup allowing easier use of multiple modules in a single header. If you plug in the module at the top of the header the the top left and right of the header are 0V and 3.3V respectively.

You can see an example of the improved header already on our Broaddown4 product

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where we also go further and 2.5V and 1.8V are also available to modules on the LHS DIL Header on this product. We are going add the simple version of this as an enhancement to Raggedstone1 in the next few months when we do a minor revision of the product. I will be asking this group for opinions in the coming few weeks for what else we could improve on this product when we do this given we are trying to meet a low cost target with the product. We will also be looking at concepts for Raggedstone2 and possibly Raggedstone3 when we do this review. These products will not replace the Raggedstone1 but will have slightly different targets but again with the low cost, value for money, theme.

John Adair Enterpoint Ltd.

Reply to
John Adair

Just to confirm that I understand correctly: to attach the EtherPHY to the Raggedstone1, I should plug it in such that the pin marked "J1" on the PHY goes in the hole marked "Y21" on the Raggedstone.

Is this correct?

Thanks again for all your help!

- a

Reply to
Adam Megacz

Adam

Not quite, the top pin of the outer run of J1 plugs into 0V and is the ground pin for the module on the older style DIL headers on the current Raggedstone1. The Y21 etc marked on board next to the headers are the pin numbers of the FPGA that the adjacent DIL pin connects to. It makes making up a UCF a bit easier as you don't have to wade through schematcs.

Schematics for the Ethernet Phy module are located here

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and will give you the module pinout.

John Adair Enterpo> "John Adair" writes:

Reply to
John Adair

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