Hi all, I'm designing a small project which uses the primitive FIFO_16 of virtex 4. The problem is: This FIFO uses an asynchronous reset, which resets all flags and internal registers of FIFO. Reset signal doesn't reset data in and data out. In my design, I have a synchronous reset and when it occurs I need to do not have an output data from FIFO. Is it enough to add some code lines, for example in the top module: if (RST) data_out_top_module
I'm not familiar with Virtex FIFOs, but I've used FIFO chips. When the FIFO is reset, its flags show that the FIFO is empty. You may get garbage when reading an empty FIFO, or you may get the previously read value. No data is written into the FIFO unless the WR pin is active. So, I'm not sure why you want to zero out data_in and data_out.
-Dave Pollum
what I want is to zero out data_out. In my case I have : If (RST) reg_b
maybe somethin like if fifo_empy = '1' then data_out
I think this begs the original question of why there needs to be any known value on the data_out when a FIFO is empty? Resetting the pointers and flags is good enough for anything I can think of. What is downstream from the FIFO that needs zero on the data_out when the FIFO is empty? Is the data itself used to indicate its own validity?
What does the OP mean by:
I need to do not have an output data from FIFO.
Zero is output data as much as any other value. The important thing to happen at reset is for the empyt flag to assert.
Just my 2 cents, Gabor
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