Field-Programmable Gate Arrays

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System Generator pcore I/O performance results

Hello all: I have a question regarding using SysGen to create a co-processor that's used in a microblaze design. I'm us...
7 comments posted 19yrs
posted by wilder_joel
7 comments posted 19yrs posted by wilder_joel

Ross Freeman - inventor of the FPGA

I understand that the inventor of the FPGA was a Ross Freeman, who died aged 45, tragically just 5 years after he co-cou...
5 comments posted 19yrs
posted by fancier.fpga
5 comments posted 19yrs posted by fancier.fpga

JTAG Tap Master (was: TI Tap Controller std8980)

I am looking for a working model of std8980 (TI Tap master) or any other tap master model. The one from FMF (http://www....
0 comments posted 19yrs
posted by akhailtash
0 comments posted 19yrs posted by akhailtash

website for chip designers

Website, which lots ot technical information both on front end and on backend topics with expertise level on each conte...
1 comments posted 19yrs
posted by chipdesignart
1 comments posted 19yrs posted by chipdesignart

SetJmp/LongJmp for Microblaze

Does anybody use Setjmp.h for Microblaze?. I have to use this library but something is wrong, so I have decided to open...
2 comments posted 19yrs
posted by pbantunez
2 comments posted 19yrs posted by pbantunez

VIrtex-4 FIFO16

Hi everybody, In the new version (2.1) of the Virtex-4 User Guide (ug070), in the FIFO chapter is described the synchro...
2 comments posted 19yrs
posted by taileb.mehdi
2 comments posted 19yrs posted by taileb.mehdi

Why I cannot use the XAUI core(generated by xilinx)

I use COREGEN to generate XAUI(choose device Virtex5 110t), but I cannot do simulation with modelsim6.1f. It is always...
2 comments posted 19yrs
posted by mynewlifever
2 comments posted 19yrs posted by mynewlifever

File open, read and write in Xilinx EDK 7.1

Hi, Iam writng a c code in Xilinx EDK 7.1 and am having problems with the fopen construct. Iam trying to read data from...
0 comments posted 19yrs
posted by acetracerbullet1000
0 comments posted 19yrs posted by acetracerbullet1000

record type port in vhdl and simulation in ISE

Hello, I have an entity in VHDL that one of its ports is a record type. I am trying to create a test bench wave form to...
2 comments posted 19yrs
posted by (use_my_name_here)-34
2 comments posted 19yrs posted by (use_my_name_here)-34

Modelsim Low and High violations

When simulating a post-routed design in ModelSim, I get a number of setup, hold, recovery violations such as: # ** Warn...
0 comments posted 19yrs
posted by mhs000
0 comments posted 19yrs posted by mhs000

Word sync in Cypress FX2 fifos /w 8 bit bus

Any Cypress FX2 (USB) gurus out there? I have one of these devices on an FPGA board (Digilent Nexys), which only provid...
5 comments posted 19yrs
posted by cs_posting
5 comments posted 19yrs posted by cs_posting

MGT Clocking

I am currently trying to free-up some DCMs for use in other parts of our design, so I am trying to make some MGTs share...
1 comments posted 19yrs
posted by mdhicks2
1 comments posted 19yrs posted by mdhicks2