Field-Programmable Gate Arrays

Question about reset signal for several DCMs in EDK design.

Hello, I have several DCMs in my design and they are phase synchronized. I generated them respectively in the DLL mode...

3 comments posted 19yrs

posted by pang.dudu.pang

3 comments posted 19yrs posted by pang.dudu.pang

Spartan 3 IOSTANDARD vs VCCO

An output pin voltage swing is determined by VCCO, so how else does specifying LVCMOS25 vs LVCMOS18 as the IOSTANDARD af...

2 comments posted 19yrs

posted by fsdgsdf

2 comments posted 19yrs posted by fsdgsdf

Regarding drivers for FPGA based PCI cards

Lately I've seen a couple of posts that ask for a PCI based prototype boards which has drivers available. Well actually...

2 comments posted 19yrs

posted by ehliar

2 comments posted 19yrs posted by ehliar

Summer with fpgas

Hi, I'm a beginner in the fpga world.I've been reading up some of the books listed in this group in other posts, and do...

18 comments posted 19yrs

posted by kunal.yadwadkar

18 comments posted 19yrs posted by kunal.yadwadkar

Altera MPM7064LC84 vs EPM7064LC84

Can anyone explain to me what the difference is between MPM7064LC84 and EPM7064LC84? Thanks, Derek

1 comments posted 19yrs

posted by dereks314

1 comments posted 19yrs posted by dereks314

Re: 64 bit matrix multplication

> hi, > i want to impliment a 64 bit floating point matrix > multplication of matrix size 256*256, in verilog. Asking t...

1 comments posted 19yrs

posted by martin.j.thompson

1 comments posted 19yrs posted by martin.j.thompson

Ask: why xilinx FPGA pin assignment couldn't pass p&r?

Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The fo...

0 comments posted 19yrs

posted by camwwang

0 comments posted 19yrs posted by camwwang

Altera M4K memory usage

Hi everybody, I'm using a Cyclone II EP2C20 which has 52 M4K memory blocks with each 4096+512bits. I want to use the wh...

2 comments posted 19yrs

posted by manfred.balik

2 comments posted 19yrs posted by manfred.balik

Question about Xilinx ISE (problem with signals trimming)

Ive got a problem like mentioned, During "map" signals that are used in the design are being trimmed and than I get err...

2 comments posted 19yrs

posted by aa

2 comments posted 19yrs posted by aa

VHDL source code for polyphase filter

Hello, Where can I find the VHDL ( or verilog) source code for polyphase filter? Is there any free implementation around...

4 comments posted 19yrs

posted by (myname_here)_123456

4 comments posted 19yrs posted by (myname_here)_123456

Any recommendation for proto PCB

Hi everybody, Currently I use www.eurocircuits.com for my standard PCB prototypes. They are cheap and rather good but t...

0 comments posted 19yrs

posted by Marc.Battyani

0 comments posted 19yrs posted by Marc.Battyani

Problems in simulation (Webpack 9.1.03i)

Finally I got simulation of logicores in webpack 9.1.03i to work with the ISE simulator. However, these messages appear...

2 comments posted 19yrs

posted by theller

2 comments posted 19yrs posted by theller

IOB and DIFFM/DIFFS

Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The fo...

0 comments posted 19yrs

posted by camwwang

0 comments posted 19yrs posted by camwwang

Issues with the BBD file, using a core generated using ISE coregenerator

Hi all, I have a few issues with how to use the BBD file. key words ISE 8.2, XPS 8.2, BBD file, CORE Generator step1. I...

1 comments posted 19yrs

posted by narashimanc

1 comments posted 19yrs posted by narashimanc

There is something (other) like his?

http://www.seventech.it/english/prodotti.php Jamma platform for gaming with SDK Thanx

0 comments posted 19yrs

posted by nomail

0 comments posted 19yrs posted by nomail