Re: 64 bit matrix multplication

Apr 19, 2007 1 Replies
M


hi,


> i want to impliment a 64 bit floating point matrix
> multplication of matrix size 256*256, in verilog.

Asking this on a VHDL newsgroup may not be the best idea... try comp.arch.fpga (given that you are thinking of using Xilinx devices) - I'll cross post this there...


kindly suggest me is
> it possible to impliment in xillinx.
>

Yes.



There are many more questions to be answered now...



For example.. How fast do you want to do it? Are you going to use internal or external memory to store your matrices? (Are there devices with 12MBit of internal BRAM...?)



My compilation's finished now, so I'm back off to the lab now...



Cheers, Martin


martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
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G

(snip)

I believe it can be done as a systolic array. I have worked on other systolic array designs, but not this one.

The OP didn't say how fast it needed to be done, which is an important parameter. That mostly tells you how many operations you need to do at once, which then tells how much hardware you need. It may be that it needs more than one FPGA, which would make more memory available.

Systolic arrays tend to use both internal and external memory, some values flowing through the pipeline, some stored internally in each processor node.

-- glen

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