Field-Programmable Gate Arrays

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License problems with Quartus 7.0 on Linux

I've been trying to use Quartus 7 on Linux (I've tried three different RedHat/Clone distros, FC6, CentOS 5, Scientific...
2 comments posted 19yrs
posted by schvantzkoph
2 comments posted 19yrs posted by schvantzkoph

computing branch metric for viterbi decoder

Hi, Hi, i saw the circuit for computation of branch metric in the following paper ( figure 3 a ), but i cant understand...
0 comments posted 19yrs
posted by engr.saqib.riaz
0 comments posted 19yrs posted by engr.saqib.riaz

Ubuntu and Webpack?

Has anyone tried to install xilinx webpack on ubuntu 6.06LTS? If I run the web download tool (sudo ./setup) I get throu...
3 comments posted 19yrs
posted by cepope
3 comments posted 19yrs posted by cepope

V5 GTP Transceivers supporting LVPECL

I have the V5 GTP transceiver differential output going to a non-xilinx receiver. The non-Xilinx receiver has following...
0 comments posted 19yrs
posted by cpandya
0 comments posted 19yrs posted by cpandya

Help with ATF750CL and WinCUPL

I'm trying to code an 'enhanced' binary-to-7segments display decoder with ATF750CL and WinCUPL. I'm experiencing proble...
2 comments posted 19yrs
posted by vento_74
2 comments posted 19yrs posted by vento_74

FF setup and hold time.

Hi, can any one please clarify me that all the FF in the FPGA has same setup time and hold time values? If not why and w...
2 comments posted 19yrs
posted by himassk
2 comments posted 19yrs posted by himassk

UCF file for LT FastDAACS board?

Does oneone have a Xilinx UCF file for the Spartan Device on the linear technology FastDAACS board, and is willing to sh...
0 comments posted 19yrs
posted by theller
0 comments posted 19yrs posted by theller

VHDL core for Hitachi H8S or H8/300H CPU?

Hi are there anybody who have knowledge about some free VHDL core for Hitachi H8S or H8/300H CPU? Regards /Michael Wilsp...
1 comments posted 19yrs
posted by michael
1 comments posted 19yrs posted by michael

About DDR SDRAM

Hi everyone! I'm working with DDR SDRAM but I don't know how to choose row address and column address. Can you help me,...
5 comments posted 19yrs
posted by gordonfreeman1983
5 comments posted 19yrs posted by gordonfreeman1983

Disable Readback (XILINX)?

If i have an external SPI FLASH connected to the FPGA and uses 'Disable Readback' in the configuration. What does it do...
2 comments posted 19yrs
posted by sven
2 comments posted 19yrs posted by sven

V5 LVPECL Inputs

I have a differential driver with Vcm = 3.025V and Differential voltage of 1100mv. Thus each arm of the differential si...
15 comments posted 19yrs
posted by cpandya
15 comments posted 19yrs posted by cpandya

EDK OPB_SPI in slave mode

Hi having trouble :(, all Xilinx and example only explain the used of OPB_SPI as master, as slave it doesnt want to work...
0 comments posted 19yrs
posted by Antti.Lukats
0 comments posted 19yrs posted by Antti.Lukats

ANNC: Power Saving Design Techniques Webcast

Lattice is holding a webcast on Tuesday, May 15, "Power Saving Design Techniques with Low Cost FPGAs." The presenter wi...
0 comments posted 19yrs
posted by bart.borosky
0 comments posted 19yrs posted by bart.borosky

ISE Simulator :Does nothing when double click

Using ISE 8.2i I have created a top-level schematic and inside of it, wired some VHDL modules (as black boxes). I made...
2 comments posted 19yrs
posted by jeloyah
2 comments posted 19yrs posted by jeloyah