Latest threads in Field-Programmable Gate Arrays

How do I constraint multiple clock cycle in Altera?

Hello everybody, My Altera design uses multiple clock cycle and negative clock edge, how do I constraint it? Here is my...

1 19yrs

newsreader

1 19yrs newsreader

How to insert tab in Write() function in VHDL

Hi, I want to insert tab in write() function in VHDL. Here is a write() function definition: procedure WRITE(L : inout...

9 19yrs

wtxwtx

9 19yrs wtxwtx

Quartus 7.1 Simulations

I have a strange issue with Quartus 7.1 simulation. I have a project with inputs a, b, c, and d. If I include inputs a,...

0 19yrs

dgrolem

0 19yrs dgrolem

I need advice

Hi all, I will be dealing with two fpga projects for school ; instructer has given some specs about these projects Coul...

1 19yrs

kemalinmaili

1 19yrs kemalinmaili

Single Chip MSX computer full schematic and VHDL sources

Hi http://code.google.com/p/fpga-retro/downloads/list there is the distribution archive for the one chip MSX project wo...

6 19yrs

Antti.Lukats

6 19yrs Antti.Lukats

Precision RTL and DesignWare libraries

Hi, I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow...

4 19yrs

edmond.cote

4 19yrs edmond.cote

Xilinx Timing Constraint Questions

I need some help making sure I constrain a design properly. The input clock to the front end logic runs at 312 MHz. Thi...

2 19yrs

mottoblatto

2 19yrs mottoblatto

How to port simulink design to FPGA?

Hi, I have a design where I have implemented a simple band pass filter found to be working even on hardware in the loop...

0 19yrs

sfoo

0 19yrs sfoo

video soltion provider

Hello, Is there any expert who can guide me about the following problem: I need video system with following main specif...

4 19yrs

mirzamihsan

4 19yrs mirzamihsan

Mobile DDR vs DDR2

Hi Folks, I need to put in DDR or DD2 interfaces. I need about 1.2GB/s bandwidth. As I am targetting a low end fpga, I...

1 19yrs

fpgabuilder-groups

1 19yrs fpgabuilder-groups

FPGA and LEGO Mindstroms

Two Students at TU Vienna (Alexander and Peter) have designed and built a very nice board to interface an FPGA (running...

0 19yrs

mschoebe

0 19yrs mschoebe

Unusual question about generic port use (optional ports??)

Hi all ... I have been writing VHDL for many years now, but can't seem to figure something out. I'm writing a component...

2 19yrs

j

2 19yrs j

Semaphores in xilkernel?

Hi, my name is Pablo and I have problems with the use of semaphores in xilkernel. I have created a struct based on pthr...

0 19yrs

pbantunez

0 19yrs pbantunez

DDR 2 Memory controller own implementattion

Hi to all ............ Now i am in to developing DDR2 memory contoller with STRATIX II EP2S 180 . Is there mega core wh...

3 19yrs

sudhakarmvs

3 19yrs sudhakarmvs

VHDL newbie: building sequential circuits with basic gates

Hey everyone, As an assignment for a course in my CS degree, I have to build a D latch, a D flip flop and a 1 bit regis...

16 19yrs

gomox.ar

16 19yrs gomox.ar

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