Field-Programmable Gate Arrays

Quartus 7.1 Simulations

I have a strange issue with Quartus 7.1 simulation. I have a project with inputs a, b, c, and d. If I include inputs a,...

0 comments posted 19yrs

posted by dgrolem

0 comments posted 19yrs posted by dgrolem

I need advice

Hi all, I will be dealing with two fpga projects for school ; instructer has given some specs about these projects Coul...

1 comments posted 19yrs

posted by kemalinmaili

1 comments posted 19yrs posted by kemalinmaili

Single Chip MSX computer full schematic and VHDL sources

Hi http://code.google.com/p/fpga-retro/downloads/list there is the distribution archive for the one chip MSX project wo...

6 comments posted 19yrs

posted by Antti.Lukats

6 comments posted 19yrs posted by Antti.Lukats

Precision RTL and DesignWare libraries

Hi, I was wondering if anyone had any experience with using Synopsys' DesignWare libraries in a Precision RTL FPGA flow...

4 comments posted 19yrs

posted by edmond.cote

4 comments posted 19yrs posted by edmond.cote

Xilinx Timing Constraint Questions

I need some help making sure I constrain a design properly. The input clock to the front end logic runs at 312 MHz. Thi...

2 comments posted 19yrs

posted by mottoblatto

2 comments posted 19yrs posted by mottoblatto

How to port simulink design to FPGA?

Hi, I have a design where I have implemented a simple band pass filter found to be working even on hardware in the loop...

0 comments posted 19yrs

posted by sfoo

0 comments posted 19yrs posted by sfoo

video soltion provider

Hello, Is there any expert who can guide me about the following problem: I need video system with following main specif...

4 comments posted 19yrs

posted by mirzamihsan

4 comments posted 19yrs posted by mirzamihsan

Mobile DDR vs DDR2

Hi Folks, I need to put in DDR or DD2 interfaces. I need about 1.2GB/s bandwidth. As I am targetting a low end fpga, I...

1 comments posted 19yrs

posted by fpgabuilder-groups

1 comments posted 19yrs posted by fpgabuilder-groups

FPGA and LEGO Mindstroms

Two Students at TU Vienna (Alexander and Peter) have designed and built a very nice board to interface an FPGA (running...

0 comments posted 19yrs

posted by mschoebe

0 comments posted 19yrs posted by mschoebe

Unusual question about generic port use (optional ports??)

Hi all ... I have been writing VHDL for many years now, but can't seem to figure something out. I'm writing a component...

2 comments posted 19yrs

posted by j

2 comments posted 19yrs posted by j

Semaphores in xilkernel?

Hi, my name is Pablo and I have problems with the use of semaphores in xilkernel. I have created a struct based on pthr...

0 comments posted 19yrs

posted by pbantunez

0 comments posted 19yrs posted by pbantunez

DDR 2 Memory controller own implementattion

Hi to all ............ Now i am in to developing DDR2 memory contoller with STRATIX II EP2S 180 . Is there mega core wh...

3 comments posted 19yrs

posted by sudhakarmvs

3 comments posted 19yrs posted by sudhakarmvs

VHDL newbie: building sequential circuits with basic gates

Hey everyone, As an assignment for a course in my CS degree, I have to build a D latch, a D flip flop and a 1 bit regis...

16 comments posted 19yrs

posted by gomox.ar

16 comments posted 19yrs posted by gomox.ar

can JTAG port of CPLD gets damaged?

i am using altera cpld.using quartus 2 tool to programme it through byte blaster cable. I have installed drivers for th...

2 comments posted 19yrs

posted by kulkarku

2 comments posted 19yrs posted by kulkarku

too brief documentation?

Currently using this board. however I kind of feel that the documentation in using the board is abit too brief http://w...

0 comments posted 19yrs

posted by csoon

0 comments posted 19yrs posted by csoon