Hello,
On my board, the FPGA receives its reset_n signal from a voltage supervisor IC (such as MAX635x or LM370x).
Is there a point to further filter (digitally) this signal upon entry into the FPGA ? Does this improve or reduce the resiliency of the design to errors / glitches / noises ?
In favor of filtering: glitches on the line between the voltage supervisor and the FPGA will be filtered.
Against filtering: (1) enforces synchronous reset, while I might want it to be asynchronous. (2) ignores a valid reset signal from the voltage supervisor when the supplies "go nuts" for the filtering time, which may lead to undesired results.
What are your thoughts ?
Thanks in advance