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Some doubts in the FPGA design flow in the ISE

Hi, I am not been able to understand the details of the each stage in the design flow. Actually what are the things happening in the mapping stage? During low-level optimization itself, XST infers specific components (is this time itself it's checking the available components in the FPGA). If I use Synplify tool for synthesis and select v4 fpga what will happen if I select the v5 in the ISE during the Mapping. Does it will select the resource that's available only in the v5?

Thanks in advance Subin

Reply to
subint
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I dont know how exactly the tool will behave. But in the synthesized output obtained from the synplify there will surely be some components which belongs to v4 only. This will generate an error in the mapping stage of the V5 based flow. In the synplify what they do is convert the behaviour model to some macros (or large functional units) first in the synthesize stage. Try some mux it will simply put a large mux there. Then in the mapping stage it will get mapped to specific LUTs or FFs etc. These selection of component is strictly deveice specific. In the ISE also i guess similar kind of flow. In my experiance several times i have mapped a design which is synthesized for v4lx60 to v4lx100 and 200 devices without any error. In this case there is no mismatch of component but no: of components only matter.

Reply to
vssumesh

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