After PAR simulation, should I assume that it will work on FPGA board?

8MHz sounds too low for an FPGA clock, not that I'm overly familiar with Xilinx devices. Check the fMin on the DCM...

Regards,

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Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Post-PAR means at least using the netlist instead of rtl code. But is useless without timing information. I assume you used timing, else start using sdf files.

Identify differences between your testbench and the real world. First thing to look: simulate asynchronous inputs switch typically with fixed delay to clock, real asynchronous inputs need proper handling.

The designflow you described seems to include all necessary steps, so I expect the problem to arise from your design.

bye Thomas

Hi Thomas,

I have only two input signals, one is the clock and another is the reset. All the signals are synchronous to the clock. Can you please explain in detail how can move ahead using sdf files, and giving timing constraints. I have presently not used any constraints other than the clock frequency.

Thanks, Sandip

Dude .. look for clues in the real world. What are you monitoring to know that the design doesn't work? Do you have any outputs? :)

Modify your design to add some debug features. For instance .. for very very basic sanity ... create an output that is a div2 of the clock and see what frequency it is in the real world. That at least tells you the FPGA has been programmed and has a valid clock.

Create some other debug points that indicate certain events of your design have occured. This may give you some insight as to where things are going wrong.

Mike