Regarding multiple write problem in opencores pci bridge

Hello there, I have been using opencores PCI core and its working very fine. If someone has already used it please clarify one thing to me.

Before I come to the problem let me explain you the setup I am using, I have master enabled silicon image Sata controller card on one of the pci slot and fpga card on the other. I have been successful in using opencores pci to configure sata card and enabling its DMA mode. I have attached 1 MB sram at PCI target side. In DMA mode sata controller reads and writes data in blocks. Basically it is using memory read multiple multiple command for reading and memory write command (CBE =

7) for writing. For writing sata controller asserts frame and IRDY for long time and continuously writes data on target.

Now the problem is that sata controllers successfully reads all the data from memory and transfer it to hard disk but once its writes data back to sram I get mismatches. I have used chipscope pro and I confirm that signal terminates properly with exact expected data on PCI bus but once wishbone master module outputs address and data it contains few errors. Can you help me with this.

With best regards Adnan