Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

OPB IPIF Master Attachment

Hello, I am trying to use the OPB IPIF Master Attachment. Does anyone know where I can find a working example of this? T...
0 comments posted 19yrs
posted by payal.kapoor
0 comments posted 19yrs posted by payal.kapoor

Topics and Ideas for BS Project

Hi friends, I am new to this forum and found that you guys are really helpful to each other with strong knowledge on FP...
18 comments posted 19yrs
posted by haghdoost
18 comments posted 19yrs posted by haghdoost

Mesa 5i21 Xilinx

Hi, I=B4m new to card using Xilinx chips. I=B4m developping a new vhd prgogram, and on one Mesa example, at the very be...
1 comments posted 19yrs
posted by mrbiancu
1 comments posted 19yrs posted by mrbiancu

System Generator installation

Hi, I'm trying to install system generator on MATLAB R2007a. I can't get pass the license agreement as the wizard keep...
0 comments posted 19yrs
posted by mloulah
0 comments posted 19yrs posted by mloulah

FFT and etc on a cycloneII or III help/sugestions.

Hello, I need some advise... I'm trying to find my way for having an FFT running on a FPGA (along with some other easy...
0 comments posted 19yrs
posted by cupidoREMOVE
0 comments posted 19yrs posted by cupidoREMOVE

modelsim

Hi does anyone already made a tcl command to write down any signals from the wave into a CSV file (excel compatible) tha...
2 comments posted 19yrs
posted by jr3002
2 comments posted 19yrs posted by jr3002

MGT Clock

Hi I am designing a board with a Virtex 4 FX20. I want to use 4 out of the MGT devices. I am planning to use a 312.5MHz...
1 comments posted 19yrs
posted by maxascent
1 comments posted 19yrs posted by maxascent

Power PC heap initialisation on Reset

Hi all, I have a SOC with a Power PC running on a Virtex II pro. On FPGA configuration, the PPC firmware runs correctly...
3 comments posted 19yrs
posted by t
3 comments posted 19yrs posted by t

ISE and total equivalent gate count

Hi, ISE's map report states a "Total equivalent gate count for design". Can this equivalent gate count be used to compa...
3 comments posted 19yrs
posted by sheinzle
3 comments posted 19yrs posted by sheinzle

Lattice XP2 finally announced

Hi finally !!! XP2 was scheduled for september 2006 so with a little less than 12 months delay its finally announced!!....
34 comments posted 19yrs
posted by Antti.Lukats
34 comments posted 19yrs posted by Antti.Lukats

any experiences concerning xup and digilent inc.?

I'm student at Chemnitz University of Technology, Germany. I'm interested in purchasing an xupv2p-board from digilent i...
2 comments posted 19yrs
posted by l.s.rockfan
2 comments posted 19yrs posted by l.s.rockfan

TBUF and modular design flow on spartan

I have a project where I am trying to use modular design flow. When I do synthesis of one of my modules I see the messa...
4 comments posted 19yrs
posted by javaguy11111
4 comments posted 19yrs posted by javaguy11111

Problem with System ACE

Hi folks, I am desperately trying to load a design via System ACE onto a ML403 board. What I use: ISE 8.2i ML403 Linux...
1 comments posted 19yrs
posted by hachti
1 comments posted 19yrs posted by hachti

Create and Import Peripheral in EDK

Hello everybody, I am trying to interface my user logic ip_inv through the OPB in EDK using a register like this: the c...
1 comments posted 19yrs
posted by koustav79
1 comments posted 19yrs posted by koustav79