Field-Programmable Gate Arrays

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linux and USB JTAG at Spartan 3e starter

Hi, I have here my brand new Spartan 3e starter kit, therefore I could test my vhdl code in real, could ... Anyway, I'm...
4 comments posted 19yrs
posted by olaf
4 comments posted 19yrs posted by olaf

Another EDK Sim question...

Sorry about multiple posts, but I am just trying to migrate a project that was once working in sim over to 9.1 tools. I...
0 comments posted 19yrs
posted by mottoblatto
0 comments posted 19yrs posted by mottoblatto

jaja

echt ofnie?
0 comments posted 19yrs
posted by pow
0 comments posted 19yrs posted by pow

Newbie Question: Using Includes in Verilog

This is a very basic question. I would appreciate your help. I have a Xilinx FPGA Verilog project that containts severa...
3 comments posted 19yrs
posted by freeagent.20.oracle
3 comments posted 19yrs posted by freeagent.20.oracle

PBGA FPGA in hi-rel application

Hi I am involved in a high reliability application where the device we want to use (Quicklogic EclipsePlus QL7160) is o...
1 comments posted 19yrs
posted by dave.bryan
1 comments posted 19yrs posted by dave.bryan

Module LOCK possible in VHDL?

Dear I want to get "actual clock frequency" of my design (in ISE tool). Due to following problem, I am having trouble....
0 comments posted 19yrs
posted by pasacco
0 comments posted 19yrs posted by pasacco

FPGA with ARM+CAN+USB+ethernet+ADC

http://www.zylogic.com.cn/english/products04.htm I wonder what that is? it looks like the product Triscend never announ...
4 comments posted 19yrs
posted by Antti.Lukats
4 comments posted 19yrs posted by Antti.Lukats

XST net splitting blocks placement

I have a Spartan 3 interfaced to a TigerSHARC via its "link port", which is a 4-bit wide DDR communications interface....
6 comments posted 19yrs
posted by dtweed
6 comments posted 19yrs posted by dtweed

TimeQuest - clocks related by default?

Hi All, It is obviously my fault, and the correct answer is probably "RTFM" (1), but I've just lost significant amount...
1 comments posted 19yrs
posted by wzab01
1 comments posted 19yrs posted by wzab01

Pin Capacitance Quartus 6.0

I have a warning with Quartus 6.0 software in the Fitter section. It says : "Found 71 ouput pins without output pin loa...
1 comments posted 19yrs
posted by fpga.vhdl.designer
1 comments posted 19yrs posted by fpga.vhdl.designer

adaptive filter FPGA

thanks for looking and please help me. I have a 16 bit ADC sampling at 50Mhz. I take only 10 MSB and display i in my vi...
11 comments posted 19yrs
posted by ckh827
11 comments posted 19yrs posted by ckh827

HELP with Asynch RAM

PLEASE HELP: In my design I have a bank of memory made up of 64 reg[31:0]'s. They get synthesized into latches, and kil...
2 comments posted 19yrs
posted by FrankTDai
2 comments posted 19yrs posted by FrankTDai

EDK Simulation Problem

I have upgraded to EDK 9.1 and am trying to generate the HDL simulation files. I have successfully compiled both the IS...
3 comments posted 19yrs
posted by mottoblatto
3 comments posted 19yrs posted by mottoblatto

another Forth CPU design

While trying to minimize my microcode implementation to implement a small 6502 CPU, eventually I designed a new Forth C...
6 comments posted 19yrs
posted by fb
6 comments posted 19yrs posted by fb

LVPECL output skew

I would like to use Virtex5 FPGA to output 16 differential channels at 800Mbps source synchronously. I am planning to u...
15 comments posted 19yrs
posted by dmoyes
15 comments posted 19yrs posted by dmoyes