Latest threads in Field-Programmable Gate Arrays

Achronix Async FPGA Silicon available when ?

I see Achronix and Mentor Graphics have inked a co-operation deal. Anyone know when their Async FPGA Silicon will actual...

0 19yrs

no.spam

0 19yrs no.spam

Want to become part of Xilinx Applications Engineering ?

If you think you meet our high standards, and you would like to work in a challenging but friendly environment in San J...

0 19yrs

peter

0 19yrs peter

Can anyone identify the manufacturer of this Chip ?

I am interested in finding the manufacturer of U3 on this SSD device: http://www.engadget.com/2007/02/19/the-do-it-your...

34 19yrs

richardrooney

34 19yrs richardrooney

MIG 7.12 DDR2 bank availibility

I'm a MIG newbie and am trying to implement the following: Memory: DDR2, 64 MB x 16 x 2 chips (64 MB x 32 result) FPGA:...

0 19yrs

urbpublic

0 19yrs urbpublic

ML402 card (video starter kit) : Read/write on the ddr

Hello everybody, I am trying to make a software video processing with the VSK. For this, I want read video data from th...

1 19yrs

oussama.hammouda

1 19yrs oussama.hammouda

Suggestions for Xilinx based evaluation board for image processing

Hello! I have been playing with image processing on FPGA for some time now, and the results seem interesting (I am work...

5 19yrs

sepher_grupy

5 19yrs sepher_grupy

DFS to generate Frequencies slightly apart

Hello, for some legacy instrument, I need to replace AM796X Taxichips doing a 9B11B encoding/decoding. The Taxichip is...

3 19yrs

bon

3 19yrs bon

How to use UART on Spartan 3E Starter Kit

Hello, Can anybody help me with some reference designs, through which I can get an insight to using UART on Spartan 3E...

4 19yrs

jaycp.iitkgp

4 19yrs jaycp.iitkgp

Interesting problems about high performance computing

There is a software application which demonds huge computation. My aim is to port the software program into hardware. S...

18 19yrs

hitsx

18 19yrs hitsx

[Announce] Linux 2.6.20 on MicroBlaze now available

Hi folks, Just a quick announcement that PetaLogix has released version 0.20 of our PetaLinux environment, which includ...

5 19yrs

jwilliams

5 19yrs jwilliams

noisy rising edge clock - non-monotonic clock

We are having some tests failing under certain clock signals. The clock signal is generated in an external device with...

2 19yrs

csisterna

2 19yrs csisterna

[ISE] how to synthesize XilinxProcessorIP/pcore

Dear I want to synthesize "opb_arbiter" in ISE. What I did was (1) Locate "opb_arbiter_v02_e" and "proc_utils_v1_00_a"...

0 19yrs

pasacco

0 19yrs pasacco

V4 PPC to sleep?

I want to put the PPC running linux in my virtex-4 to sleep to save power. Apparently, the official software suspend me...

0 19yrs

cepope

0 19yrs cepope

MIG for Virtex-4 DDR dimm, only 165 Hz?

Hello, Why does Xilinx MIG controller support DDR dimm at only 165 MHz in Virtex-4 ? (175MHz in -12). I remember seeing...

2 19yrs

prdubois

2 19yrs prdubois

Weird behavior in debuggin using XMD

I have implemented a base builder system for the Spartan3e starter kit where i have a TestApp_memory.c which is downloa...

1 19yrs

kislo02

1 19yrs kislo02

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