I'm a MIG newbie and am trying to implement the following:
Memory: DDR2, 64 MB x 16 x 2 chips (64 MB x 32 result) FPGA: XC4VLX25-10FF668
The DDR2 I/O requirements can be satisfied using one 'big' bank (banks
5-10) and one 'small' bank (banks 1-4). My plan was to allocate data, control and address to bank 5 and address to bank 3.In the MIG GUI, when I select a big bank (5), all DDR2 signal groups are supported (address, data, control). However, when I select a small bank (3), only the control lines are supported. In this case, the address and data lines won't all fit in the large bank, so I get an error indicating that not enough pins are available for the address lines.
When looking at bank 3, there doesn't appear to be any reason why it shouldn't be availble. Unlike banks 1,2, DCI is available on banks 3,4 for the the LX25-FF668.
I haven't yet looked at the generated HDL code to see if there are come clock distribution issues with bank 3 that make it unavailable, but I wouldn't suspect this is the issue.
Any ideas???
TIA Urb