Virtex4 ISERDES question

I am simulating a verilog design that uses Virtx4 ISERDES primitive. This design requires the "O" ouput pin of the Virtx4 ISERDES primitive. The "O" pin in the Virtx4 ISERDES primitive provides a copy of D input or delayed copy of D input. Now I am transitioning my design to Virtex5. Virtex5 ISERDES primitive does not seem to support the "O" output pin. This is a timing sensitive design and wanted to know clean way to do this in Virtex5. Why this pin was removed from Virtex5 ISERDES module? What was its original purpose in Virtex4?

What is the best way to handle this? Is it as simple as using a buf to get the signal and use it?

Thanks for your help.


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