Field-Programmable Gate Arrays

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Rocket IO clocking

I have a problem with the RocketIO component. The documentation says that I need a differential clock for the Rocket IO...
3 comments posted 19yrs
posted by sego
3 comments posted 19yrs posted by sego

Question about xilinx jtag programmer

Does anyone know what it means pinout compatible to UFS / Twister / N-Box / Power Flasher & Other compatible gsm interfa...
2 comments posted 19yrs
posted by <darrick>
2 comments posted 19yrs posted by <darrick>

Add DMA support to a custom core?

Hi everyone. I have a core to control a I/O peripheral. This core is based on a FIFO to get words from a I/O bus (32 bi...
4 comments posted 19yrs
posted by pbantunez
4 comments posted 19yrs posted by pbantunez

Simulation problem

Hi all, I wrote a generate loop to generate a switching logic. I am getting the expected circuit from the synthesizer(s...
4 comments posted 19yrs
posted by subin.82
4 comments posted 19yrs posted by subin.82

USB full speed final project proposal

I invite you to use free code of a USB full speed project as final work for diploma. The site includes some description...
0 comments posted 19yrs
posted by bknpk
0 comments posted 19yrs posted by bknpk

Spartan-3e JTAG no device id

I am trying to get an xc3s250e-4tq144c to configure using JTAG. 1. impact reads 0x00000000 as idcode This causes impact...
22 comments posted 19yrs
posted by alan
22 comments posted 19yrs posted by alan

MPC 8321E DDR2 interface

i am using MPC 8321E POWER PC ,can any one tell me how to interface 2GBYTE DDR2 SDRAM. problem is it has only 32 bit dat...
1 comments posted 19yrs
posted by anandraj7k
1 comments posted 19yrs posted by anandraj7k

Xilinx DCM Reset

I have been reading through UG331 for information on the DCM, especially in the case with external clock feedback. On a...
10 comments posted 19yrs
posted by pladow
10 comments posted 19yrs posted by pladow

DIFF_TERM Question

For a Xilinx V4, there is an IBUFDS_DIFF buffer that you can use in the I/O pad. However, it appears that there is no d...
3 comments posted 19yrs
posted by mottoblatto
3 comments posted 19yrs posted by mottoblatto

Metastability in very slow clock domains

Hi, Lets say we have a signal crossing from a high frequency clock domain into a low frequency clock domain, where the...
6 comments posted 19yrs
posted by jon
6 comments posted 19yrs posted by jon

Microblaze and software interrupts?

Hi all, I'm developing a multicore system with up to four Microblaze cores. Now I'm searching for a solution to inform...
8 comments posted 19yrs
posted by hofmann.juergen
8 comments posted 19yrs posted by hofmann.juergen

question about xilinx jtag

My socket seems not to be in the documentation. It looks a bit like those sockets of harddisk cables expect there are ju...
1 comments posted 19yrs
posted by <darrick>
1 comments posted 19yrs posted by <darrick>

Xilinx PCI Express solutions

Hi All, does anybody has any experience with the Xilinx Philips PX1011A solutions? Thanks in advance, Francesco
1 comments posted 19yrs
posted by francesco_poderico
1 comments posted 19yrs posted by francesco_poderico