Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

New with FGPAs

Hello, I've just started a small project with a Xilinx Virtex 4FX board. In general terms my objective is to read vario...
3 comments posted 19yrs
posted by ryufrank
3 comments posted 19yrs posted by ryufrank

I need relocate my program outside bram...

I'm developing an embedded web server into a XupV2pro board with a VirtexII-pro fpga. While all my code was in the bram...
1 comments posted 19yrs
posted by periket2000
1 comments posted 19yrs posted by periket2000

USB analyzer evaluation

hi all experts could you recommend good USB analyzer for me i am an new USB driver developer and my boss wanted me to i...
1 comments posted 19yrs
posted by hobin0920
1 comments posted 19yrs posted by hobin0920

Multiple Core generator MAC FIR Filter 5.1 Cores

Hello all, I am trying to generate several MAC FIR Filter cores for the same project. The filters range in length from...
5 comments posted 19yrs
posted by vt2001cpe
5 comments posted 19yrs posted by vt2001cpe

Doubt in Asynchronus Circuit design

Hi All, I am designing my first real clock domain crossing circuit. My problem is a high speed wrapper for a low speed...
13 comments posted 19yrs
posted by vssumesh_asic
13 comments posted 19yrs posted by vssumesh_asic

Spartan-3A: 200A & 400A Image problems / variance...

Hello Group. Having a home-made PCB board which can adopt to both Spartan-3A XC3S200A and XC3S400A FPGAs in the same FB...
2 comments posted 19yrs
posted by Jesper.Kristensen
2 comments posted 19yrs posted by Jesper.Kristensen

Does synplify 8.8 can support xilinx virtex5?

I use synplify 8.8 to synthesis my design. And my design contain xilinx ip core (generated by core generator). My desig...
2 comments posted 19yrs
posted by azzhang2007
2 comments posted 19yrs posted by azzhang2007

Revisit: Altera vs Xilinx (NIOS II vs Microblaze)

Hi everyone, No doubt this subject has been discussed on numerous occasions: http://www.embeddedrelated.com/groups/fpga...
44 comments posted 19yrs
posted by pretzel_n_g
44 comments posted 19yrs posted by pretzel_n_g

Power PC Reference Design timing failed

Recently, I download a reference design from Xilinx. Then implementate in EDK9.1.02i, while checking the timing report,...
1 comments posted 19yrs
posted by Jarod2046
1 comments posted 19yrs posted by Jarod2046

Xilinx V4/V5 FPGA SATA GTP

V4 FPGA has independently RXSIGDET port signal,but V5 not. how to detect the signal on V5 GTP?
3 comments posted 19yrs
posted by water9580
3 comments posted 19yrs posted by water9580

Can't get Actel tools to run on SL4.4 (RHEL 4.4)

Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scien...
0 comments posted 19yrs
posted by schvantzkoph
0 comments posted 19yrs posted by schvantzkoph

ICAP in V4 FX20 only working after Reset

Hello, I am trying to use the ICAP module of a Virtex-4 FX20. I built a project with EDK8.1 using the OPB-ICAP module f...
3 comments posted 19yrs
posted by ahnews
3 comments posted 19yrs posted by ahnews

LVDS via Emulation

Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks n...
1 comments posted 19yrs
posted by yy7d6
1 comments posted 19yrs posted by yy7d6

read/write in bram block

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component. i hav...
2 comments posted 19yrs
posted by rajivc53
2 comments posted 19yrs posted by rajivc53