Spartan-3A: 200A & 400A Image problems / variance...

Hello Group.

Having a home-made PCB board which can adopt to both Spartan-3A XC3S200A and XC3S400A FPGAs in the same FBGA320 footprint, we are having great troubles getting the 400A image of the logic to work stable, while the 200A image seems to work perfectly with the same logic. The symptoms are that various bits or groups of bits seem to "hang" whenever we try to get them on the uController Bus for reading etc..

We have tried using both Xilinx ISE 8.2 and 9.1 as Fitter, but with the same non-stable, although *different* result in respect of which bits cannot be reached.

The 3 I/Os being the difference between the two Spartan-3A variants are *not* connected in the PCB. Voltages are correct, and the timing should absolutely be no problem in the design (Fmax 4 times over). We have no troubles loading the FPGA devices in two different configurations. The problems seems consistent among boards with the same FPGA - 200A or 400A.

- Have you heard of such problems...?

- Or do you just have some type of clue...?

Thanks in advance,


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The kind of problem you mention is often an issue of poor timing where asynchronous boundaries are crossed improperly and the unconstrained timing path is simply different between the two place & routes, not so much 200A vs 400A. Your timing report can generate more than a constrained-path timing report which must show proper compliance to your needs; you can generate a list of unconstrained paths as well.

Maybe something important was forgotten in the timing constraints you did intend to specify and you'll discover what that was when you generate the unconstrained paths.

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Also take a look at the Vccint supply to make sure you're not getting supply droop. With the same design loaded, the dynamic power will be about the same for the 400A as the 200A, but the static power will be higher in the 400A, perhaps enough to make a voltage difference.

Also note that in a larger part it is easier to get large routing delays on unconstrained paths. Another headache with larger parts in the same package is that pin to pin delays can vary significantly because the larger part will not necessarily place adjacent IOB's where there were adjacent IOB's in the smaller part. Usually once the IOB's in the silicon exceed the bonding for the package you start to see large groups of unbonded IOB's between adjacent bonded IOB's in the middle of a bank.

Good Luck, Gabor

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