V4 FPGA has independently RXSIGDET port signal,but V5 not.
how to detect the signal on V5 GTP?
Xilinx V4/V5 FPGA SATA GTP
Jul 05, 2007
3 Replies
Page 155
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You need to configure the "loss of Sync (LOS) state machine for the standard you wish to use.
Austin
i think it should be RXLOSSOFSYNC[0] representation incoming data. right?
thx your help.
You might want to take a look at RXELECIDLE in table 7-5 (p130, UG196 v1.3). Like RXSIGDET, it goes high when the RX differential voltage drops below the minimum threshold voltage for an OOB signal.
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