Field-Programmable Gate Arrays

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Question on Virtex2p DCMs usability

Greetings, First off, let me share with you that I'm a complete newb when it comes to FPGA/ISE/VHDL. I'm using the "fre...
5 comments posted 19yrs
posted by nospam
5 comments posted 19yrs posted by nospam

fifo counter in virtex-4

I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and...
3 comments posted 19yrs
posted by bjzhangwn
3 comments posted 19yrs posted by bjzhangwn

ML555 SFP module

I use Xilinx PCSPMA GTP IP core to connect ML555 SFP interface. But how to connect the signal_detect signal of PCSPMA GT...
3 comments posted 19yrs
posted by water9580
3 comments posted 19yrs posted by water9580

XilinxSystemGenerator and Simulink

Hi, I've been working on a simulink model built using the Xilinx Blockset to try to verify the function of an interplat...
4 comments posted 19yrs
posted by cwoodring
4 comments posted 19yrs posted by cwoodring

XPS 8.2 "UPDATE Tcl procedures"?

Hi, all. Can anyone tell me what "Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC..." means, and...
1 comments posted 19yrs
posted by the.jd.in.space
1 comments posted 19yrs posted by the.jd.in.space

verilog code for read write in Bram block

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component.i have...
3 comments posted 19yrs
posted by kahnani
3 comments posted 19yrs posted by kahnani

or1k binutil source checkout problem

i've checked out the binutils for or1k from opencores.org. the downloaded files contain two files with .diff extensions...
0 comments posted 19yrs
posted by e2point
0 comments posted 19yrs posted by e2point

multiprocessor design-shared memory-howto

I'm dealing with a multiprocessor board design. The major issue is speed. Processors should be connected to a ring but...
0 comments posted 19yrs
posted by piclist9
0 comments posted 19yrs posted by piclist9

sdr woes

Hi all, I am trying to build a sdr to demodulate am signals. i am using xilinx dds to generate my local oscillator sign...
0 comments posted 19yrs
posted by bhargavalluri
0 comments posted 19yrs posted by bhargavalluri

Debugging in EDK

Hi i am debuggin a simple program running on the Spartan3e starter kit : int main() { int k = 3; int i = 2; int j = 4;...
2 comments posted 19yrs
posted by kislo02
2 comments posted 19yrs posted by kislo02

ML555 SATA GTP dosen't work

My SATA host controller includes TX/RX OOB Sequence generation ciruit(it can generate COMRESET/COMINIT/COMWAKE). My GTP...
2 comments posted 19yrs
posted by water9580
2 comments posted 19yrs posted by water9580

ML501 Constraints file problems

Hello, I'm testing ML501 board, very nice. On the Xilinx site the documentation of this board has some errors like the...
1 comments posted 19yrs
posted by callisto.pili
1 comments posted 19yrs posted by callisto.pili

New with FGPAs

Hello, I've just started a small project with a Xilinx Virtex 4FX board. In general terms my objective is to read vario...
3 comments posted 19yrs
posted by ryufrank
3 comments posted 19yrs posted by ryufrank

I need relocate my program outside bram...

I'm developing an embedded web server into a XupV2pro board with a VirtexII-pro fpga. While all my code was in the bram...
1 comments posted 19yrs
posted by periket2000
1 comments posted 19yrs posted by periket2000