XilinxSystemGenerator and Simulink

Hi, I've been working on a simulink model built using the Xilinx Blockset to try to verify the function of an interplation filter made from the MacFir Core. The full working VHDL version of the complete data path where the input data goes into a fifo and is read out to the filter as it is ready for data. The filter does a simple up by 2 interpolation and the output data is written to another fifo for eventual output. This filter actually handles 64 channels. The input rate for the data is 100KHz and the Output rate is to be

200KHz. In my simulink model I read the data for a input signal consisting of 2 sine waves, one well within the filters passband and one in the stop band, from the MATLAB workspace. I then multiplex that same data to 28 channels and feed the filter which is intantiated in the Simulink model as a black box as per Matlab's help file for inserting a Xilinx core into a model. I've had a lot of confusion about sample rates and how to deal with them in Simulink, but I think I'm finally getting the hang of them. The output rate is 2x the input rate for the complete system - fifo in to fifo out but the filter runs very fast compared to the actual data rate in and out. The Modelsim simulation of the whole VHDL coded system seems to be working- I get 2 samples out for every one in on all the channels and the data is written to the output fifos ok. Since the data is fixed point I wanted to verify my output values with what I get in the Simulink model which uses the fixed point blockset etc. The biggest issue I have is that the Modelsim simulation goes very fast and outputs data from the filter every usec or less while the Simulink model using the Modelsim output block takes milliseconds to produce an output data. It does give me 2 values for every one in and the filter model appears to be working ok, but the clocking of the whole model is running at a sample rate of 100KHz. . I use modelsim under the control of Simulink to run the simulation and the fastest clock in the simulation is 200KHz. The system clock in the "real" VHDL system is 80MHz. When I try to increase the system clock in the SystemGenerator block to anything faster than 1MHz I get some error about an unresolved Boolean value and the simulation doesn't run. Has anyone matched what an actual synthesizable system to a Simulink model at the actual clock rates used in the VHDL simulation? When I look at all the example files for simulink it seems they always use sample rates of 1sec which seems ridiculous when trying to match clock rates in an FPGA system. Am I really off the mark here or to I just have to run my Simulink model for 45 minutes to match what the VHDL model gives me in 2 seconds?

Totally dazed and confused,

CTW

Reply to
cwoodring
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There are different ways to handle the clocks in System Generator. It can be confusing.

If your real clock is going to be 80MHz, create a variable T_system_clock = 1/80e6 in your Matlab workspace. Use this variable in your System Generator token. Now make sure that the clock rates in your system are all integer multiples of this clock. For example, if your FIR input runs at 100kHz, set the sample period of the filter = (1/100e3)/T_system_clock. This will be an integer multiple of the system clock. Now in the Simulink 'Simulation Stop Time' you put N*T_system_clock where N is the number of clock cycles which you want to run the simulation for. The times shown in a scope window for example will match the actual time related to the 80MHz clock in hardware.

Basically the clock that is specified in the System Generator token must be equal to the fastest clock in your system, the slower clocks will all be generated with CE's by System Generator and you will not get errors about clocks that are not integer clock cycles of the system clock.

One more thing, use the FIR Compiler and not the MAC FIR as it will be replaced by the FIR Compiler.

Hope this helps

Reply to
naude.jaco

Thank you for the reply however I did what was suggested - In the System Generator Block I have the sample period set to 1/80e6 where I defined SystemClk as 80e6, and for the filter I have it set to (1/100e3) = 10e-6 =

800/SystemClk. When I view the sample rates in the model I see 800 for the inputs to the filter and 400 for the outputs. This seems ok to me. I do get a message window stating that the simulink period is too small for the rates used in the model and that a better value would be 1/100e3. When I run the simulation I never get past the 0ps point and I get the error stating Boolean type output port op gets indeterminate value but it doesn't specify which block actually caused it. The message states the default block is the source? A second error states Error reported by S-function "sysgen" in filt/BlackBox. Summary of errors from all sources. None of the errors was associated with a particular block; the block reported was chosen at random? If I redefine SystemClk to 1e6 then the simulation will run but certainly won't match the real VHDL simulation. Yesterday by editing the config.m file for the filter I eventually got the model to run for 5 microseconds using the 80MHz clk. There are 3 clks showing up in Modelsim, the 80MHz, a 200KHz (400*(1/TSystemclk), and a 100KHz.(800*(1/TSystemClk) but it looked like at the first transiti>> Hi,
Reply to
cwoodring

Hi,

The message window stating that the simulink period is too small for the rates used in the model and that a better value would be 1/100e3 sounds normal if you don't have anything running at the 80MHz frequency. Simulink will notice this and let you know that a better setting would be the fastest rate used in your design. Thus the filter rate. Using the 80MHz clock frequency as the sample period in your SysGen token might not be the best option if you don't have anything running at that frequency as this will increase the simulation times in Simulink quite significantly. It depends if you want it to match your VHDL simulation or not. What I normally do is I take the fastest frequency in my design. When looking at the spectrum of any signal in my design I can see the full -Fs/2 to Fs/2 bandwidth of that signal and also all the slower signals in my design.

I'm not 100% sure what you mean with the errors that you are getting. Remember that you have to correctly specify output rates on a black box. This might be causing the problems...

FIR Compiler is in Coregen and is used in System Generator when you drop the FIR Compiler block into your design.

Hope this helps. Cheers

Reply to
Jaco Naude

On Jul 9, 3:41 am, snipped-for-privacy@gmail.com wrote:

Hi all,

I'm using sysgen to implement my design. I've already designed a group of 5 filters, using sysgen, which I'm using to pre-process my data, which works fine. However I still have some confusion with it. The input to these filtering stages is a file which contains data sampled at 200 hertz(samples per second). If I enter the simulink system period in the xilinx block to a value between 0.2s to 2s, the design works. However, for any value lower than 0.3s the design fails completely. I donno what this sytem period implies in actual terms, but it doesn't make any sense to me at all, given that the sampling period of my data should be 1/200, which doesn't work. This is one part of the problem. In the second phase I added 4-5 black box modules to my current design, which basically plays with the pre-processed data obtained from the above filtering stages. Now, When I connected everyting together, I got an error that there's some problem with the sample rate and types in the feed back loops between the modules. I used the hints given with the errors, by introducing assert and delay block, to get rid of these nagging errors and I specifically provided the sample rate to be equal to that of the output from the filtering stages. Now this helped me in getting rid of all the errors involving algebraic errors in the loops etc. However, the output that I get is pretty crappy. Something doesnt seem to be right, with the sample rates as I already tested my vhdl code in modelsim, and they worked fine. Long story short, Can anybody please help me solve this issue of specifying the sample rate in sysgen both in the sysgen block and black boxes. I followed the instructions given on this page too, however, just like the cwoodring, even I couldn't get it to work. The filter behaves in a weird manner and doesn't look like its giving the right output unless the simuling sample time is set to 1, which is ridiculous. Please respond if you have any clue as to what's goin wrong. Thanx in advance.

Reply to
ashishshuklabs

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