verilog code for read write in Bram block

Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component.i have written verilog code for bram controller .i have to call this verilog code by a c programe. C code is:

#include "stdio.h" #include "xparameters.h" #include "xuartlite_l.h" #include "mb_interface.h"

int main(void) { int i,j,k; int *mem; int fill_value = 0x10000001;

//basic uart test print ("hello world\r\n"); for (k=0;k

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You could try declaring "mem" as volatile;

volatile int *mem; mem= (volatile int*)0x10000032;



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Hi all, This is the verilog code which i have written to read and write from bram block but when i am reading from it i get only zero and nothing else.So can anyone please suggest changes.I have given c code also for your refrence.

module user_logic ( // -- ADD USER PORTS BELOW THIS LINE --------------- // --USER ports added here

IP2Bus_Clk, // IP to Bus clock Bus2IP_Clk, // Bus to IP clock Bus2IP_Reset, // Bus to IP reset IP2Bus_IntrEvent, // IP to Bus interrupt event Bus2IP_Addr, // Bus to IP address bus Bus2IP_Data, // Bus to IP data bus for user logic Bus2IP_BE, // Bus to IP byte enables for user logic Bus2IP_Burst, // Bus to IP burst-mode qualifier Bus2IP_RNW, // Bus to IP read/not write Bus2IP_RdCE, // Bus to IP read chip enable for user logic Bus2IP_WrCE, // Bus to IP write chip enable for user logic Bus2IP_RdReq, // Bus to IP read request Bus2IP_WrReq, // Bus to IP write request IP2Bus_Data, // IP to Bus data bus for user logic IP2Bus_Retry, // IP to Bus retry response IP2Bus_Error, // IP to Bus error response IP2Bus_ToutSup, // IP to Bus timeout suppress IP2Bus_RdAck, // IP to Bus read transfer acknowledgement IP2Bus_WrAck, // IP to Bus write transfer acknowledgement Bus2IP_MstError, // Bus to IP master error Bus2IP_MstLastAck, // Bus to IP master last acknowledge Bus2IP_MstRdAck, // Bus to IP master read acknowledge Bus2IP_MstWrAck, // Bus to IP master write acknowledge Bus2IP_MstRetry, // Bus to IP master retry Bus2IP_MstTimeOut, // Bus to IP mster timeout IP2Bus_Addr, // IP to Bus address for the master transaction IP2Bus_MstBE, // IP to Bus byte-enables qualifiers IP2Bus_MstBurst, // IP to Bus burst qualifier IP2Bus_MstBusLock, // IP to Bus bus-lock qualifier IP2Bus_MstRdReq, // IP to Bus master read request IP2Bus_MstWrReq, // IP to Bus master write request IP2IP_Addr // IP to IP local device address for the master transaction

); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------ // --USER parameters added here // -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE -------------------- // -- Bus protocol parameters, do not add to or delete parameter C_AWIDTH = 32; parameter C_DWIDTH = 32; parameter C_NUM_CE = 6; parameter C_IP_INTR_NUM = 1; // -- DO NOT EDIT ABOVE THIS LINE --------------------

// -- ADD USER PORTS BELOW THIS LINE ----------------- // --USER ports added here // -- ADD USER PORTS ABOVE THIS LINE -----------------

output IP2Bus_Clk; input Bus2IP_Clk; input Bus2IP_Reset; output [0 : C_IP_INTR_NUM-1] IP2Bus_IntrEvent; input [0 : C_AWIDTH-1] Bus2IP_Addr; input [0 : C_DWIDTH-1] Bus2IP_Data; input [0 : C_DWIDTH/8-1] Bus2IP_BE; input Bus2IP_Burst; input Bus2IP_RNW; input [0 : C_NUM_CE-1] Bus2IP_RdCE; input [0 : C_NUM_CE-1] Bus2IP_WrCE; input Bus2IP_RdReq; input Bus2IP_WrReq; output [0 : C_DWIDTH-1] IP2Bus_Data; output IP2Bus_Retry; output IP2Bus_Error; output IP2Bus_ToutSup; output IP2Bus_RdAck; output IP2Bus_WrAck; input Bus2IP_MstError; input Bus2IP_MstLastAck; input Bus2IP_MstRdAck; input Bus2IP_MstWrAck; input Bus2IP_MstRetry; input Bus2IP_MstTimeOut; output [0 : C_AWIDTH-1] IP2Bus_Addr; output [0 : C_DWIDTH/8-1] IP2Bus_MstBE; output IP2Bus_MstBurst; output IP2Bus_MstBusLock; output IP2Bus_MstRdReq; output IP2Bus_MstWrReq; output [0 : C_AWIDTH-1] IP2IP_Addr; // -- DO NOT EDIT ABOVE THIS LINE --------------------

//---------------------------------------------------------------------------- // Implementation //----------------------------------------------------------------------------

// --USER nets declarations added here, as needed for user logic

// Nets for user logic slave model s/w accessible register example reg [0 : C_DWIDTH-1] slv_reg0; reg [0 : C_DWIDTH-1] slv_reg1; reg state,nextstate; wire [0 : 1] slv_reg_write_select; wire [0 : 1] slv_reg_read_select; reg [0 : C_DWIDTH-1] slv_ip2bus_data; wire slv_read_ack; wire slv_write_ack; integer byte_index, bit_index;

wire [0:31] DOA_BRAM; wire [0:3] DOPA_BRAM; reg [0:14] ADDRA_BRAM; reg [0:31] DIA_BRAM; reg [0:3] DIPA_BRAM; reg [0:3] WEA_BRAM; wire [0:31] DOB_BRAM; wire [0:3] DOPB_BRAM; reg [0:14] ADDRB_BRAM; reg [0:31] DIB_BRAM; reg [0:3] DIPB_BRAM; reg [0:3] WEB_BRAM; `define ENA_BRAM=1'b1; `define ENB_BRAM=1'b0; initial state=1'b0;

// --USER logic implementation added here

// ------------------------------------------------------ // Example code to read/write user logic slave model s/w accessible registers // // Note: // The example code presented here is to show you one way of reading/ writing // software accessible registers implemented in the user logic slave model. // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond // to one software accessible register by the top level template. For example, // if you have four 32 bit software accessible registers in the user logic, you // are basically operating on the following memory mapped registers: // // Bus2IP_WrCE or Memory Mapped // Bus2IP_RdCE Register // "1000" C_BASEADDR + 0x0 // "0100" C_BASEADDR + 0x4 // "0010" C_BASEADDR + 0x8 // "0001" C_BASEADDR + 0xC // // ------------------------------------------------------

assign slv_reg_write_select = Bus2IP_WrCE[0:1], slv_reg_read_select = Bus2IP_RdCE[0:1], slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1], slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1];

// implement slave model register(s)

always @( posedge Bus2IP_Clk ) begin state=nextstate; end always @(posedge Bus2IP_Clk) begin: SLAVE_REG_WRITE_PROC

if ( Bus2IP_Reset == 1 ) begin slv_reg0 = 32'h10000000) ADDRA_BRAM = slv_reg0 & 32'h300007ff;

if( slv_reg_write_select==1'b1) nextstate=1'b1; // in case of write else WEA_BRAM =4'b0000; // in case of read end

1'b1 : // for getting data begin for ( byte_index = 0; byte_index
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Again, if you must use the OPB why not use the Xilinx provided opb_bram_if_cntlr? It should save you the hassle of debugging your Verilog. There is no reason to re-invent the wheel.

I still recommend using the lmb_bram_if_cntrl if it's an option.

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