Re: ESR Meter - Roll your own - ESRrev0.JPG

"john jardine" wrote:

John Larkin wrote: >> Something roughly like this, maybe. This is a 2-minute hack, so >> don't jump all over it right away; a real design would take more >> time. >> Basically, it's an oscillator that dumps current into the cap, >> and a synchronous detector to remove most of the orthogonal >> component. It ain't perfect, but should be a lot better than a >> scalar measurement. >> John > This was built along similar lines. The synchronous rectification > is not perfect due to phase shift in the forward signal path but > the arrangement is useful for reducing the annoying capacitive > quadrature component from Q's up to about 3 (at the 100kHz). It's > usable down to the milliohm area and proved the (cheap) 1000 off > 10uF cap's I bought, had an ESR of between 1 and 3 ohms!.

Hi John,

Do you mind if I make some comments? The 1 ohm resistor, R5, can be removed from the circuit. It is at a virtual ground node and has little or no voltage across it. So removing it has little effect on the circuit.

With R5 gone, and the ESR range switch in the 1 ohm position, the 180 ohm resistor, R4, is effectively in series with the capacitor under test. The op amp merely changes the location of the ground node, and inverts the output signal polarity.

Since R4 (180 ohms) is now in series with the capacitor, it completely swamps out the internal ESR (0.05 ohms.) This means the series combination of C, L, and R has negligible "Q", and there is no quadrature or orthogonal component in the circuit.

However, as the ESR decreases, the corresponding voltage drop that we are trying to measure also decreases. We no are faced with the problem that the di/dt from the inductor is much larger than the I*R drop from the ESR. This means the leading and trailing edge of the square wave have large spikes.

If you used a diode peak detector to measure the amplitude, it would respond as best it could to the leading edge spike, which would make it impossible to measure the drop across the ESR. Your circuit and Larkin's share this problem.

Using a synchronous rectifier helps a bit, but you are now faced with trying to turn it on after the leading edge spike, and to turn it off before the trailing edge spike. That could be tricky.

I spent this afternoon looking at these problems in SPICE, and have come to an amazing observation. There is a hidden but very significant feature in the bridge ESR circuit referred to at the beginning of this thread. The links are:

  1. Talino Tribuzio's page, showing the circuit from Nuova Elettronica:

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  1. Gintaras' web page, who refers to Tribuzio's page in his readme

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The schematic is at

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The valuable hidden feature is the bridge configuration completely eliminates the leading and trailing edge spikes due to the capacitor internal inductance. Since the spikes are in phase with the square wave signal on the other side of the bridge, they simply disappear at the output of the op amp!

This means the peak detector has a very clean square wave to work with, and it can give a much more accurate measurement of the signal. There is no tricky timing to fiddle with that can go out of whack just when you need to use the tester.

If you like, I can post the analysis of your circuit and Larkin's version showing the huge spikes that appear as the ESR becomes smaller, and the triangular wave from the capacitance charging and discharging. I don't really see a good way of overcoming these problems.

As I mentioned in previous posts, the bridge circuit has significant advantages, including low test voltage, in-circuit test, shorted capacitor detect, etc. With the extremely clean output signal into the peak detector, it becomes the obvious choice for hassle-free ESR measurements.

I'll post the LTspice ASC file here along with the PLT file so you can see how it works. I changed the bridge resistance to lower values to allow measuring lower values of ESR.

Here's the LTspice ASC file:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Version 4 SHEET 1 880 708 WIRE -496 -112 -528 -112 WIRE -368 -112 -416 -112 WIRE -304 -112 -368 -112 WIRE -192 -112 -224 -112 WIRE -368 -96 -368 -112 WIRE -128 -80 -160 -80 WIRE -48 -64 -64 -64 WIRE -720 -48 -816 -48 WIRE -704 -48 -720 -48 WIRE -592 -48 -624 -48 WIRE -528 -48 -528 -112 WIRE -528 -48 -592 -48 WIRE -368 -48 -528 -48 WIRE -192 -48 -192 -112 WIRE -192 -48 -288 -48 WIRE -128 -48 -192 -48 WIRE -816 -32 -816 -48 WIRE -160 0 -160 -80 WIRE -160 0 -240 0 WIRE 128 16 96 16 WIRE 224 32 192 32 WIRE 240 32 224 32 WIRE 336 32 304 32 WIRE -528 48 -592 48 WIRE -240 48 -240 0 WIRE -240 48 -448 48 WIRE -224 48 -240 48 WIRE -96 48 -144 48 WIRE -48 48 -48 -64 WIRE -48 48 -96 48 WIRE 32 48 16 48 WIRE 128 48 32 48 WIRE -816 64 -816 48 WIRE 32 128 32 48 WIRE -720 144 -720 -48 WIRE -704 144 -720 144 WIRE -592 144 -592 48 WIRE -592 144 -624 144 WIRE -512 144 -592 144 WIRE -416 144 -448 144 WIRE -304 144 -336 144 WIRE -192 144 -224 144 WIRE -592 160 -592 144 WIRE -192 160 -192 144 WIRE 96 176 96 16 WIRE 208 176 96 176 WIRE 336 176 336 32 WIRE 336 176 208 176 WIRE 208 192 208 176 WIRE 336 208 336 176 WIRE 32 224 32 208 WIRE -592 256 -592 240 WIRE -464 272 -480 272 WIRE -432 272 -464 272 WIRE -272 272 -288 272 WIRE -240 272 -272 272 WIRE -480 288 -480 272 WIRE -288 288 -288 272 WIRE 208 288 208 272 WIRE 336 288 336 272 WIRE -480 384 -480 368 WIRE -288 384 -288 368 FLAG -96 48 DIFF FLAG -592 256 0 FLAG -192 160 0 FLAG -816 64 0 FLAG -368 -96 0 FLAG -592 -48 E2P FLAG -592 48 E2N FLAG 32 224 0 FLAG 336 288 0 FLAG 208 288 0 FLAG 336 32 DC FLAG -480 384 0 FLAG -464 272 VCC FLAG -288 384 0 FLAG -272 272 VEE FLAG 224 32 VOP FLAG 32 48 VIN FLAG 160 0 VCC FLAG 160 64 VEE FLAG -96 -96 VCC FLAG -96 -32 VEE SYMBOL res -608 144 R0 SYMATTR InstName R8 SYMATTR Value {Rb} SYMBOL res -608 128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R9 SYMATTR Value {Rt} SYMBOL cap -448 128 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C3 SYMATTR Value {C} SYMBOL res -320 128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R10 SYMATTR Value {ERS} SYMBOL ind -320 160 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L3 SYMATTR Value {L} SYMBOL Voltage -816 -48 R0 WINDOW 0 42 44 Left 0 WINDOW 3 -22 -62 Left 0 WINDOW 123 15 130 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PULSE(0 4 0 {Tr} {Tr} 5u 10u) SYMBOL res -608 -64 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R5 SYMATTR Value {Rt} SYMBOL res -512 -96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R11 SYMATTR Value {Rb} SYMBOL res -320 -96 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R12 SYMATTR Value 47k SYMBOL res -384 -32 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R13 SYMATTR Value 1k SYMBOL res -544 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R14 SYMATTR Value 1k SYMBOL res -240 64 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R15 SYMATTR Value 47k SYMBOL cap 16 32 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C4 SYMATTR Value 2n SYMBOL res 16 112 R0 SYMATTR InstName R16 SYMATTR Value 47k SYMBOL diode 240 48 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL cap 320 208 R0 SYMATTR InstName C5 SYMATTR Value 2nf SYMBOL res 192 176 R0 SYMATTR InstName R17 SYMATTR Value 470k SYMBOL Opamps\\1pole 160 32 R0 SYMATTR InstName U1 SYMATTR Value2 Avol=1Meg GBW=100Meg Slew=100Meg SYMBOL Voltage -480 272 R0 WINDOW 0 42 44 Left 0 WINDOW 3 47 72 Left 0 WINDOW 123 15 130 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 10 SYMBOL Voltage -288 384 R180 WINDOW 0 42 44 Left 0 WINDOW 3 47 72 Left 0 WINDOW 123 15 130 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 10 SYMBOL Opamps\\1pole -96 -64 R0 SYMATTR InstName U2 SYMATTR Value2 Avol=1Meg GBW=100Meg Slew=100Meg TEXT -528 -224 Left 0 ;'Tribuzio Bridge ESR Circuit TEXT -528 -184 Left 0 !.tran 0 2.2m 2m 100n TEXT 32 -200 Left 0 !.param C = 100uF\n.param L = 2.533E-08\n.param ERS =

0.00005\n.param Rt = 100\n.param Rb = 1\n.param Tr = 100n

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Here's the PLT file:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ [Transient Analysis] { Npanes: 3 Active Pane: 1 { traces: 1 {268959746,0,"V(dc)"} X: ('µ',0,0,2e-005,0.0002) Y[0]: (' ',3,0,0.003,1) Y[1]: ('_',0,1e+308,0,-1e+308) Volts: (' ',0,0,0,0,0.003,1) Log: 0 0 0 GridStyle: 1 }, { traces: 1 {268959747,0,"V(diff)"} X: ('µ',0,0,2e-005,0.0002) Y[0]: (' ',1,-1,0.2,1) Y[1]: ('_',0,1e+308,0,-1e+308) Volts: (' ',0,0,2,-1,0.2,1) Log: 0 0 0 GridStyle: 1 }, { traces: 1 {268959748,0,"V(e2n)"} X: ('µ',0,0,2e-005,0.0002) Y[0]: ('m',0,0,0.002,0.04) Y[1]: ('_',0,1e+308,0,-1e+308) Volts: ('m',0,0,0,0,0.002,0.04) Log: 0 0 0 GridStyle: 1 } }

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Regards,

Mike Monett

Reply to
Mike Monett
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John, wrt the alytus.auksa.lt schematic -- I don't see exactly how it can work. Considering its complete symmetry: two 22-ohm resistors to ground and 4.5mA square-wave drive, identically on each D.U.T. pin, there can be no current through the capacitor. Are we looking at the same drawing?

Reply to
Winfield Hill

Win,

If you are referring to

formatting link
the right side of the capacitor, the CAP2 pin on J6, goes to ground, and not to the junction of R12 (1K) and R17 (22).

The left side of the cap is connected to the left side of the bridge, at the junction of R11 (1K) and R16 (22).

There seems to be an optical illusion that makes you believe the cap is connected across the bridge, and I made the same mistake the first time I looked at it. But of course, it wouldn't work if it was connected that way.

The cap really is connected from the left side of the bridge to ground.

Regards,

Mike Monett

Reply to
Mike Monett

iz7ath says the esr tester circuit came from an Italian magazine, Nuova Elettronica N212. It would be interesting to see their writeup, because its operation seems backwards to me. If no capacitor is connected, the bridge is balanced, and there's no signal to the meter, which reads 0. With a capacitor connected the bridge becomes unbalanced. A perfect capacitor, esr = 0 ohms, maximally unbalances the bridge, and presumably pushes the meter to full scale. A poor capacitor reads slightly less than full scale. For example, with esr = 1 ohm (which is not a very good capacitor by today's standards) we still get a nearly full-scale meter reading, because 1 ohm is so much less than 22 ohms, and is still pretty close to zero ohms by comparison. So the meter is hard to read, showing little change for various capacitor esr values in the sub-1-ohm region of interest. In fact, 1-ohm and 0.1 ohm capacitors would have nearly the same reading. Not good!

Reply to
Winfield

The same meter was published by Marvin Smith in the July 2001 edition of Poptronics. A quick google search found many references to the Poptronics article, but no copy of it. I know it's the same meter since I have a PDF copy of the Poptronics article.

Mike

When truth is absent politics will fill the gap.

Reply to
Mike

We'd love to see a copy of the article. Failing that, a posting of the relevant portion of the meter-reading interpretation and of the circuit-operation explanation would be helpful. Be sure to include the author's full names for credit.

Reply to
Winfield

Ok, I posted the article on a.b.s.e along with a link to a totally different meter that was sold by Dick Smith electronics. I'd be interested to hear any comments on the Dick Smith version.

Mike

If there is no absolute truth then nothing can be known.

Reply to
Mike

The DSE meter was designed by Bob Parker, an aussie with a good head on his shoulders. The meter has been marketed as both a kit (best bang for the buck) and fully assembled and tested models. Most service techs that I know and those that have posted on the sci.electronics.repair NG swear by this meter. I bought and built a kit a number of years ago, and still use it. It's paid for itself many times over in the time that I've owned it.

I understand the Dick Smith has stopped selling the meter, but Bob has found other outlets for it. John's Jukes

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in Canada sells them (that's where I bought my copy).

I don't think you'll find a bad note from anyone about this meter.

--
Dave M
MasonDG44 at comcast dot net  (Just substitute the appropriate characters in the 
address)

"In theory, there isn't any difference between theory and practice.  In 
practice, there is."  - Yogi Berra
Reply to
DaveM

I'd love to have one of those meters. The design seems respectable, and the most sensitive range, 0.00 to 0.99 ohms, looks ideal for working with serious switching-supply capacitors. I see it uses a 50mA test current and amplifies the resulting esr signal by about 25x before presenting it to a comparator, the other side of which gets a slow 20V/ms ramp (9.5uA and 470nF), to measure the signal.

The difference between Bob Parker's design for Dick Smith Elec., and the Marvin Smith esr meter we were discussing is dramatic.

Reply to
Winfield

Since lots of single-chip uPs include decent adc's these days, why not just digitize the voltage drop across the cap? One could then note the cap charging slope and untangle it from the true esr. And measure capacitance, for free.

John

Reply to
John Larkin

buck)

Sure,however I think the sensitivity of the typical 10 bit ADC in a cheap micro is about an order of magntitude too low, so you need a preamp anyway.

Reply to
SP

buck)

That's about right, but it's still going to be simpler than most of the goofy and truly terrible "esr" meters we've seen here lately.

You may as well measure leakage and dielectric absorption while you're at it; code is cheap.

John

Reply to
John Larkin

Granted they are amateurish junk, but your designs and ideas are so

*ugly* they are borderline grotesque. When you have something artful to suggest that will be the day....
Reply to
Fred Bloggs

You don't approve of my products? Show us some of yours.

John

Reply to
John Larkin

As they say, I don't have to be a chef to know the food stinks...

Reply to
Fred Bloggs

Show us something you've designed.

John

Reply to
John Larkin

You show us an esr meter that doesn't require a VMX crate.

Reply to
Fred Bloggs

I suggest we have an esr-meter design contest. However, to make it usenet friendly, and accessible to the readers, all entries must be made in ASCII drawings, annotated with text.

Reply to
Winfield

Why not make it a group project, for real? I'd be willing to do the first cut at schematic and algorithms. What we really need is someone to hack the real code; I hate to program, and I'm going to do it most of the weekend likely [1], so I'm not going to volunteer for that part!

I'm sure Fred would make valuable design contributions.

But no ASCII art! We can just post sketches to abse.

John

[1] statistical analysis of some FPGA configuration patterns, leading up to a fast, small compression/decompression algorithm. We need to fit an application program and 8 megabits of Xilinx config stuff into a 4 mbit Eprom.
Reply to
John Larkin

I think Xilinx has some stuff on their site regarding compressing FPGA patters. IIRC, they're quite compressible, easily (RLL or some such).

--
  Keith
Reply to
krw

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