I'm dealing with a multiprocessor board design. The major issue is speed. Processors should be connected to a ring but they don't have dedicated ports (similar with Serial Rapid IO on TI DSPs see here
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). Each processor can address up to 2Gbytes of external SRAM/SDRAM memory and 1Mbyte of internal L2 memory. The goal is to connect the nodes on the ring (see basics here:
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) so every node could address the shared memory
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and data may flow between any pair of nodes. How will you address the shared memory to achieve the goal ?thx, Vasile