Field-Programmable Gate Arrays

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World's 1st FPGA Centric Portal goes LIVE!!

FPGA Central is the central place to find complete information about FPGA Vendors, FPGA Products, IPs, FPGA Events, FPG...
0 comments posted 19yrs
posted by vkr101
0 comments posted 19yrs posted by vkr101

camera module interface to FPGA

hi I am trying to interface a camera module to FPGA board. i am new to VLSI. can any suggest and help me out of where t...
1 comments posted 19yrs
posted by srimankk
1 comments posted 19yrs posted by srimankk

Spartan 3E starter kit DDR SDRAM

I am relying to the older "Spartan 3E starter kit DDR SDRAM code Options" thread. Is there such a demo out, mentioned i...
5 comments posted 19yrs
posted by fpgaengineerfrankfurt
5 comments posted 19yrs posted by fpgaengineerfrankfurt

V4FX PPC suspend/resume

We want to be able to save our PPC state to ram, shut off our fpga, and be able to restore the PPC when we wake up late...
5 comments posted 19yrs
posted by cepope
5 comments posted 19yrs posted by cepope

Download the contents of the FPGA's RAM block

I have FPGA DSP design that has several RAM blocks. What is the easiest way to transfer the content of the RAM to the PC...
6 comments posted 19yrs
posted by maricic
6 comments posted 19yrs posted by maricic

Forwarding engines

Evnin' Does someone knows of any books or other reading material which covers the design and implementation of forwardin...
0 comments posted 19yrs
posted by me
0 comments posted 19yrs posted by me

V4 DSOCM always reads back zeroes

Hello, I have a ML403 PPC design (XPS 9.1) that executes code out of DDR. I added 16 KByte of on chip data side BRAM, b...
1 comments posted 19yrs
posted by jcc
1 comments posted 19yrs posted by jcc

Inputs as an Array in Verilog??

Hi Guys: I am working on an application where I have a large number (264) inputs to a single Verilog module. Each input...
1 comments posted 19yrs
posted by eromlignod
1 comments posted 19yrs posted by eromlignod

Position at The MathWorks

The MathWorks has an open position for an HDL Applications Engineer. http://www.mathworks.com/company/jobs/opportunitie...
0 comments posted 19yrs
posted by ali.behboodian
0 comments posted 19yrs posted by ali.behboodian

DOSFS for EDK

In an earlier thread complaining about the state of the Xilinx website, Antti (by mistake?) signed off with a URL thus:...
2 comments posted 19yrs
posted by jcr_alr
2 comments posted 19yrs posted by jcr_alr

Writing data to bram with microblaze

Hello, I have a microblaze design which includes two bram with microblaze' bram. I want to write the addresses of dip_s...
1 comments posted 19yrs
posted by mfgunes
1 comments posted 19yrs posted by mfgunes

Static Timing Analysis Using Primetime for FPGAs

Hi, Has anyone recently done a comparision of the utility of Primetime vs. Xilinx or Altera timing analysis engines? An...
13 comments posted 19yrs
posted by ctaniguchi1
13 comments posted 19yrs posted by ctaniguchi1

help on basics of ethernet interface

hi all I am a newibe. i am tring to send bit stream data through ethernet. i am using altera DE2 board. i have my data...
0 comments posted 19yrs
posted by srimankk
0 comments posted 19yrs posted by srimankk

Xilinx Webpack for Linux 64 bit?

Does there exist a 64-bit Linux version of Xilinx Webpack? I see the programming tools are available for Linux as 64-bi...
3 comments posted 19yrs
posted by cole
3 comments posted 19yrs posted by cole