Hello,
I would like to utilize a controller for a SINGLE data rate SDRAM (Micron MT48LC16M16A2TG-75, to be specific). In the past I've used Xilinx' MiG 1.4 to obtain a DDR2 controller, which I ended up pretty happy with (after forgetting the via dolorosa to set it up...). Its main benefit is a simple and convenient FIFO-based user interface.
For some reason, I thought that MiG would create an SDR controller as well (it's simpler, after all), but it turned out I'm very wrong: The last piece of attention on Xilinx' behalf to SDR, which I've managed to find, is xapp134. That paper, along with its HDL code, originates in 1999, and is more or less the same ever since. The controller offered is hence adapted to Virtex-I and Spartan-II, and is yucky is several respects.
Newer application notes (as well as MiG) relate to faster memory classes (DDR, DDR2, QDR, you name it), with controllers eating up some clock resources to solve timing problems. And all I wanted was a cheap memory with reasonably simple access.
Given the situation, I'm considering to create a DDR controller with MiG for a memory with similar attributes (bus width, array size, etc) and then hack it down to SDR. Since the command interface is the same, that should leave me with changing the data flow, and make the burst timing right. Not much fun, but hey, after debugging the MiG DDR controller, I should survive this one as well.
And here's the irony: I picked this SDRAM to make things simpler for me.
So before I start this little self torture, does anyone have a better idea?
Thanks, Eli