Hi,
I am having some trouble with implementing several serial links per IO Bank in Virtex5. An IO bank is about the same size as a clock region. Each clock region has 4 BUFIO and 2 BUFR available. I am trying to implement 4 serial links by utilizing 4 BUFIOs and 2 BUFRs in one clock region and the 2 other BUFRs from a neighboring clock region. However, everytime I try to specify the clock region for the BUFIO and BUFR I get mapping errors.
The UCF looks like:
#Locations for BUFIO INST "RX/BUFIO" AREA_GROUP = "BUFIO_0"; AREA_GROUP "BUFIO_0" RANGE = CLOCKREGION_X0Y3; #Location for BUFR INST "RX/BUFR" AREA_GROUP = "BUFR_0"; AREA_GROUP "BUFR_0" RANGE = CLOCKREGION_X0Y2;
I get an error message during mapping where it says that the structure is locked and the relative placment of the locked logic violates the desired structure. The problem was found due to the relative placement of BUFIO and BUFR.
I wonder if anyone has tried to do similar implementations or have come across such problems. Basically, Im trying to find out if I can use the BUFR from the neighboring clock region and how to assign them.
Thank you in advance, Aida