Field-Programmable Gate Arrays

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mixed Verilog/VHDL in ispLever 7.0 broken

G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHD...
2 comments posted 19yrs
posted by me
2 comments posted 19yrs posted by me

SATA OOB using Rocket IO (Virtex 5)

Hi All, Does anyone have information on using Rocket IO of Virtex 5 for SATA OOB. I would be grateful if anyone can sen...
0 comments posted 19yrs
posted by mkumarsampath
0 comments posted 19yrs posted by mkumarsampath

edk + spi

hi is there a reason why the clock divisor for the spi clock in edk 9.1 cant be smaller than 16? i would need 4. is ther...
2 comments posted 19yrs
posted by u_stadler
2 comments posted 19yrs posted by u_stadler

new xilinx forums

http://forums.xilinx.com/ are open if someone didnt notice yet Antti
0 comments posted 19yrs
posted by Antti.Lukats
0 comments posted 19yrs posted by Antti.Lukats

Using Virtex-II Pro MGT with external CDR

Hi, I would like to know if anyone has experience with connecting an external CDR or CPA to a Virtex RocketIO MGT. I am...
0 comments posted 19yrs
posted by jeff.johnson.au
0 comments posted 19yrs posted by jeff.johnson.au

Design Behavior affected by use of Chipscope

Hello everyone, I have encountered a rather strange behavior in one of my FPGA Designs. i have a DDR2 RAM controller (g...
2 comments posted 19yrs
posted by Michael.Niegl
2 comments posted 19yrs posted by Michael.Niegl

Problems using xilfatfs on XUP V2Pro board

Hi there, I've been using the Xilinx University Program Virtex-II Pro development board and I'm having great trouble wr...
2 comments posted 19yrs
posted by pgp
2 comments posted 19yrs posted by pgp

Xilinx 13th August opportunity

quote from Xilinx webpage: "Xilinx is upgrading its forum software. These forums, along all their content, will be reti...
7 comments posted 19yrs
posted by Antti.Lukats
7 comments posted 19yrs posted by Antti.Lukats

edk+uclinux ??? <about make dep>

what's wrong with following word??? [root@localhost uClinux-dist]# make dep make ARCH=microblaze CROSS_COMPILE=mb- -C l...
4 comments posted 19yrs
posted by kobelai15
4 comments posted 19yrs posted by kobelai15

regarding the clock issues in the fpga...

hi all, i have got one problem: i have designed sonet sts-3c framer/deframer where it works at 155mhz freq which i am g...
3 comments posted 19yrs
posted by ekavirsrikanth
3 comments posted 19yrs posted by ekavirsrikanth

LUT distributed memory in FPGA devices

I wanted to add to the thread at http://groups.google.co.uk/group/comp.arch.fpga/browse_thread/thread/336b60da5f0091/c7...
3 comments posted 19yrs
posted by tlenomade
3 comments posted 19yrs posted by tlenomade

Used Stratix II FPGA's

Hi, Where can one get used Stratix II FPGA's. Thanks, Eswar Saladi email : snipped-for-privacy@gmail.com
0 comments posted 19yrs
posted by eswar.saladi
0 comments posted 19yrs posted by eswar.saladi

ucf editor edk

hi i have a question. do i have to edit the ucf file by hand in edk 9.1 or is there a editor like in ise? i thought i c...
1 comments posted 19yrs
posted by u_stadler
1 comments posted 19yrs posted by u_stadler