Design Behavior affected by use of Chipscope

Hello everyone,

I have encountered a rather strange behavior in one of my FPGA Designs. i have a DDR2 RAM controller (generated partly with the Memory Interface Generator) in a Xilinx Virtex-4 FX60. After startup it sends out some dummy patterns and reads them back to adjust the delay between issuing a command to the RAM and the execution. When I don't probe exactly these signals in the FPGA with Chipscope then this procedure is only executed sporadically, i.e. most times after configuration or a global reset the RAM controller never finishes its init-procedure (even when using an identical bit-file the success of the initialization can differ when configuring the FPGA another time). When I do use Chipscope however, it is executed everytime, so the use of it definitely influences the design. So the question is now, what could be the reason for it? Could it be a placement issue of the IODELAY elements used for the interface to the RAM or any other FPGA primitives that interface to it? If anyone had any guesses or ideas what could be the main influence I'd be happy to hear them, as I obviously would like to have the design running stably without needing Chipscope included.

Cheers, Michael

Reply to
MNiegl
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You probably have a timing problem in your design.

Make sure you run trace on your design with the -u option. This will flag any unconstrained paths. Pursue them with extreme prejudice.

Also make sure you interface signals have been mapped to IOB flip-flops. You can tell by looking at the .pad file.

When you go from chipscope (working) to non-chipscope, do you see a change in which signals are mapped to IOB FFs?

If a FF output only drives an I/O pad, it can be placed in an IOB FF. However, if the output is also added to chipscope, then feedback to internal logic is required, and the FF can not be added to an IOB FF.

The three reports to get very familiar with are your .mrp, your .pad, and your .report.

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Regards,
John Retta
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Reply to
John Retta

Hi John, As far as I can tell until now I think it is an issue of the placement of the FFs in the datapath to the RAM. I think next I will try to find a stable configuration (w. Chipscope) and then directly lock the placement of these FFs, we'll see if that helps. I'll probably get back to you once I have more news.

Thanks & Cheers, Michael

Reply to
MNiegl

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