I have a design where I use a 40MHz input clock to create a 40MHz,
80MHz, and two variable-frequency output clocks. The variable- frequencies are 80/120, 40/60, 20/30, 10/15, 5/7.5, and 2.5/3.75 respectively. The major design utilization is as follows: 9 BUFGMUX_VIRTEX4, 2 BUFG, 1 DCM_ADV, 3 PMCD.When attempting to integrate this clock generation block into our existing design, I receive a warning #438 during routing. I found Xilinx answer record 23873, which seems to be a problem similar to what I'm seeing. I'm just somewhat wary of the proposed solution, which is using 4 BUFGMUX's as 2:1 clock muxes and then a final 4:1 output mux based on regular logic. Has anyone else had this problem, and, if so, was this proposed fix used to solve it?