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Implementing MIPS Memory Hiarchy

Hi there,

I have a more general question about processor design, hope that is alright ;)

I am just implementing some kind of MIPS core, and I am about to integrate the memory hiarchy with instruction and data cache which is linked to a SRAM that contains the binary. So I was thinking of having one module for each the data and instruction cache which are both connected to the SRAM module. In this case I need two datawrite, dataread signals, one from each cache to the memory is that right? In addition, when a cache miss occurs I was thinking of stalling the pipeline for 2 clock cycles until the cache has been updated with the memory content. Is this a proper approach?

Cheers, Roman

Reply to
Roman Zeilinger
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Can't see the need for the instruction cache to write to memory.

How wide is each cache line? Often you want to make it multiple words.

Other than that, it is normal to stall the pipeline while refilling the cache, although a goal is to try an minimize how often and for how long this occurs.

Init funny that ARM/MIPS used to make millions selling something students/beginners now design.

Cheers, Jon

Reply to
Jon Beniston

Good point;)

For a start I wanna simulate the basis behaviour, and as soon as this is running smoothly I will take the next step. Lets say the wide of the cache line is 8 words, in this case I need a sram to bus interface with

8*wordsize to transfer it in one clock cycle. Or does the cache fetch a line on a word by word basis?

Cheers, Roman

Reply to
Roman Zeilinger

Usually wordsize is 32-bits, so, if you want to implement this for real, most FPGA boards will have 32-bit SRAM, so you will need to do the transfer in several cycles. Nothing unusual about that.

How are you going to perform uncached accesses to peripherals? I'd recommend having a bus between the cache and SRAM, although perhaps you want to keep it simple at this stage.

If you want to look at some example source code, look at the Lattice Mico 32.

Cheers, Jon

Reply to
Jon Beniston

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