Hi friends
i have a question regarding ISE Webpack (7.1 to 9.1 versions): Is it possible to override the value of a VHDL generic (e.g. for the top-level module under synthesis)??? Does there exist such option that can be be applied either interactive or from command-line (or both?)
This would be a very useful feature and other synthesis tools (for ASICs) do have such option.
Thank you in advance
Nikolaos Kavvadias